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single-chip 5+1-port 10/100/1000 mbps switch controller with dual mac interfaces datasheet rev. pre-1.4 19 oct. 2007 track id: realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsin chu 300, taiwan tel.: +886-3-578-0211. fax: +886-3-577-6047 www.realtek.com.tw RTL8366S/sr
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller ii track id: rev. pre-1.4 copyright ?2007 realtek semiconductor corp. all rights reserv ed. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval sys tem, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without war ranty of any kind, neither expressed nor implied, including, but not limited to, the particular purpo se. realtek may make improvements and/or changes in this document or in the product described in this d ocument at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respe ctive owners. using this document this document is intended for the hardware and soft ware engineer?s general information on the realtek RTL8366S/sr chips. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide. in that event, pleas e contact your realtek representative for additional information that may help in the development proces s. revision history revision release date summary pre-1.0 2007/03/30 preliminary release. pre-1.1 2007/04/16 enhance function description and correct some features typo. remove pins strapping function in led_p4_2, led_p3_ 2, led_p3_0, led_p2_2, led_p0_2, led_p1_0, and led_p0_0. change pins name of stestg0/1/2, stestl0/1/2, stest t, stesth, stestckp/n, stestop/n, and stestip/n to sgnd, svddl , svddt, svddh, sdckp/n, sdtxp/n, and sdrxp/n. figure 8, fig ure 9, table 2, table 3, table 5, and table 16. add serdes interface pin description and mode selec tion in section 6.2 and 9.4. add led_p4_2/reserved pin description for normal op eration. add configuration strapping pins description in sec tion 6.6. remove chapter 3 and enhance application example in chapter 4. add 1000base-x application example circuit in figur e 25. enhance general purpose interface description in se ction 9.3. revise figure 3, block diagram of RTL8366S/sr. pre-1.2 2007/05/11 revise applications block diagram, figure 4, figure 5, figure 6, and figure 7.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller iii track id: rev. pre-1.4 change the led_p4_0/disblink description in section 8.20. use pin floating to disable and pull down to enable power on blinkin g function. remove the original section 8.12.4. change the description in section 8.12.4, which onl y insert pvid for untagged or change priority tagged packets to be pvid. pre-1.3 2007/08/03 correct the configure description in section 6.3. c hange the configuration name from sel_p5mode[2:0] to sel_p5mode[1:0] add the thermal characteristics in section 11.3 add the rgmii/gmii/mii timing characteristics in se ction 11.5.3 and 11.5.4 corrected the feature of jumbo frame supporting in section 2 corrected the smi signal description of figure 1. & figure 2. corrected ?disblink? to ?enblink? in figure 8, page 22, figure 9, page 23, table 2, page 25, table 3, page 27, table 11, page 40, table 13, page 41, and section 8.20, page 61. corrected the default values of register 0,4, 5, 6, 7, 9, 15. in section 10.1, 10.5, 10.6, 10.7, 10.8, 10.10, 10.12. corrected the gmii pins ?100mbps? in section 6.3.1, page 30 to ?100mbps/10mbps; corrected ?dvddio1? , ?dvddio2?to ?dvddio0?, ?dvddi o1? in section 11.2, page 79. correct the feature description ?one port 1000base- x serdes & support utp/fiber? to ?port 4 support 1000base-x serdes or utp? combine table 15 and original table.12. modified the pin name ?swr_fb?, ?en_swr?, ?vswn?, ? vswp?, ?vphase? to ?test_fb?, ?en_test?, ?vtestn?, ?vtestp ?, ?vphtest? in table 15. appended the driving ability to table 4, page 29,30 , table 5, page 30, table 6, page 31, 32, table 7, page 33, table 8, page 33, 34, table 9, page 35, 36, table 10, page 37,38, 39, table 11, page 40, 41 tab le 12, page 41, 42, table 13, page 42, 43. deleted ?swrvddh,?, ?swrgnd? from table 41. corrected the eeprom size from 512 bytes to 2048 by tes in section 2, page 15. pre-1.4 2007/10/09 corrected the priority queue from 6 queues to 4 que ues in section 1, page 13, section 2, page 15, section 8.13, page 58, section 8.13.4, page 60.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller iv track id: rev. pre-1.4 table of contents 1. general description................................ ................................................... ................................................... ...... 12 2. features........................................... ................................................... ................................................... ......................14 3. block diagram...................................... ................................................... ................................................... ............. 16 3.1. b lock d iagram of RTL8366S/sr ........................................ ................................................... ...................................16 4. applications....................................... ................................................... ................................................... .................17 4.1. 5 port 1000b ase -t s witch ................................................... ................................................... .................................... 17 4.2. 5-p ort 1000b ase -t s witch , 5 th p ort s upport 1000b ase -t/1000b ase -x ................................................. ............ 18 4.3. 5 port 1000b ase -t r outer with d ual mii/rgmii .......................................... ................................................... ..... 19 4.3.1. port 5 mac and port 4 phy in mii/rgmii mode........ ................................................... .............................................19 4.4. 5 port 1000b ase -t r outer with o ne gmii (o ne a rm r outer ) .................................................. ........................... 20 5. pin assignments .................................... ................................................... ................................................... ............. 21 5.1. RTL8366S p in a ssignments (lqfp164) .......................................... ................................................... .......................21 5.2. RTL8366Sr p in a ssignments (lqfp216).......................................... ................................................... .....................22 5.3. p in a ssignment t able ................................................... ................................................... .......................................... 23 5.3.1. pin type conventions ............................... ................................................... ................................................... ...............23 5.3.2. RTL8366S (lqfp164) pin assignment table ............ ................................................... ................................................ 24 5.3.3. RTL8366Sr (lqfp216) pin assignment table........... ................................................... ............................................... 26 6. pin descriptions ................................... ................................................... ................................................... ............. 29 6.1. m edia d ependent i nterface p ins ................................................... ................................................... ....................... 29 6.2. s erdes i nterface p ins ................................................... ................................................... .......................................... 30 6.2.1. fiber serdes pins.................................. ................................................... ................................................... ................... 30 6.3. g eneral p urpose i nterfaces (o nly for RTL8366Sr) ......................................... .................................................. 3 0 6.3.1. gmii pins .......................................... ................................................... ................................................... ......................31 6.3.2. rgmii pins......................................... ................................................... ................................................... ..................... 33 6.3.3. mii interface pins................................. ................................................... ................................................... ................... 35 6.4. led p ins ................................................... ................................................... ................................................... ..............41 6.5. m iscellaneous p ins ................................................... ................................................... ..............................................42 6.6. c onfiguration s trapping p ins ................................................... ................................................... ............................ 43
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller v track id: rev. pre-1.4 6.7. t esting p ins ................................................... ................................................... ................................................... ........ 45 6.8. p ower and gnd p ins ................................................... ................................................... ............................................45 7. physical layer function description................ ................................................... ...................................47 7.1. mdi i nterface ................................................... ................................................... ................................................... .... 47 7.2. 1000b ase -t t ransmit f unction ................................................... ................................................... ..........................47 7.3. 1000b ase -t r eceive f unction ................................................... ................................................... ............................. 47 7.4. 100b ase -tx t ransmit f unction ................................................... ................................................... .........................47 7.5. 100b ase -tx r eceive f unction ................................................... ................................................... ............................ 48 7.6. 10b ase -t t ransmit f unction ................................................... ................................................... .............................. 48 7.7. 10b ase -t r eceive f unction ................................................... ................................................... .................................48 7.8. a uto -n egotiation for utp................................................ ................................................... ....................................48 7.9. c rossover d etection and a uto c orrection ................................................... ................................................... ...48 7.10. p olarity c orrection ................................................... ................................................... ........................................... 49 8. switch function description........................ ................................................... .............................................. 50 8.1. r eset ................................................... ................................................... ................................................... .................... 50 8.1.1. hardware reset ..................................... ................................................... ................................................... .................. 50 8.1.2. software reset ..................................... ................................................... ................................................... ....................50 8.2. 802.3 x f ull d uplex f low c ontrol ................................................... ................................................... .................... 51 8.3. h alf d uplex f low c ontrol ................................................... ................................................... ................................51 8.3.1. back pressure mode ................................. ................................................... ................................................... ............... 52 8.3.2. defer mode ......................................... ................................................... ................................................... ..................... 52 8.4. s earch and l earning ................................................... ................................................... ........................................... 52 8.5. svl and ivl/svl ............................................ ................................................... ................................................... ...... 53 8.6. i llegal f rame f iltering ................................................... ................................................... ...................................... 54 8.7. ieee 802.3 r eserved g roup a ddresses f iltering c ontrol ................................................... .............................. 54 8.8. b roadcast /m ulticast /u nknown da s torm c ontrol ................................................... ....................................... 55 8.9. p ort s ecurity f unction ................................................... ................................................... ...................................... 55 8.10. mib c ounter ................................................... ................................................... ................................................... ......55 8.11. p ort m irroring ................................................... ................................................... ................................................... .. 55 8.12. vlan f unction ................................................... ................................................... ................................................... .. 56 8.12.1. port-based vlan .................................... ................................................... ................................................... ............ 56 8.12.2. ieee802.1q tag-based vlan .......................... ................................................... ................................................... . 57 8.12.3. protocol-based vlan ................................ ................................................... ................................................... ......... 57 8.12.4. port vid........................................... ................................................... ................................................... ................... 58
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller vi track id: rev. pre-1.4 8.13. q o s f unction ................................................... ................................................... ................................................... .....58 8.13.1. input bandwidth control ............................ ................................................... ................................................... ........ 59 8.13.2. priority assignment ................................ ................................................... ................................................... ............59 8.13.3. priority queue scheduling.......................... ................................................... ................................................... ........59 8.13.4. 802.1p/q and dscp remarking ........................ ................................................... ................................................... .60 8.14. acl f unction ................................................... ................................................... ................................................... .....60 8.15. igmp&mld s nooping f unction ................................................... ................................................... .........................61 8.16. 802.1 x f unction ................................................... ................................................... ................................................... .. 61 8.16.1. port-based access control.......................... ................................................... ................................................... ........62 8.16.2. mac-based access control ........................... ................................................... ................................................... .....62 8.17. g uest vlan ............................................... ................................................... ................................................... ...........62 8.18. 802.1d f unction ................................................... ................................................... ................................................... . 62 8.19. rtct ............................................... ................................................... ................................................... ........................ 63 8.20. led i ndicator ................................................... ................................................... ................................................... .... 63 8.21. i nterrupt for e xternal cpu................................................ ................................................... ................................. 64 9. interface descriptions............................. ................................................... ................................................... ...65 9.1. eeprom smi h ost to eeprom............................................. ................................................... ................................65 9.2. eeprom smi s lave for e xternal cpu ................................................ ................................................... ...............66 9.3. g eneral p urpose i nterface (o nly for RTL8366Sr) ......................................... ................................................... . 67 9.3.1. port 5 mac gmii mode interface (1gbps)............. ................................................... ................................................... 67 9.3.2. port 5 mac and port 4 phy rgmii mode (1gbps) ....... ................................................... ........................................... 69 9.3.3. port 5 mac and port 4 phy mii mac/phy mode interfac e (100mbps)........................................ ............................. 70 9.4. s erdes i nterface ................................................... ................................................... .................................................. 7 1 10. register descriptions.............................. ................................................... ................................................... .....73 10.1. p age 0: pcs r egister (phy 0~4)............................................... ................................................... ..............................73 10.1.1. register 0: control ................................ ................................................... ................................................... .............74 10.1.2. register 1: status ................................. ................................................... ................................................... ............... 75 10.1.3. register 2: phy identifier 1....................... ................................................... ................................................... .........76 10.1.4. register 3: phy identifier 2....................... ................................................... ................................................... .........76 10.1.5. register 4: auto-negotiation advertisement......... ................................................... ................................................. 76 10.1.6. register 5: auto-negotiation link partner ability .. ................................................... .............................................. 77 10.1.7. register 6: auto-negotiation expansion............. ................................................... ................................................... 78 10.1.8. register 7: auto-negotiation page transmit register ................................................... ...........................................78 10.1.9. register 8: auto-negotiation link partner next page register .......................................... ..................................... 79
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller vii track id: rev. pre-1.4 10.1.10. register 9: 1000base-t control register ............ ................................................... .................................................. 7 9 10.1.11. register 10: 1000base-t status register............ ................................................... ................................................... 80 10.1.12. register 15: extended status ....................... ................................................... ................................................... ....... 80 11. electrical characteristics ......................... ................................................... .............................................. 81 11.1. a bsolute m aximum r atings ................................................... ................................................... ............................... 81 11.2. r ecommended o perating r ange ................................................... ................................................... ........................81 11.3. t hermal c haracteristics ................................................... ................................................... ...................................82 11.3.1. lqfp 216 ........................................... ................................................... ................................................... ................ 82 11.3.2. lqfp 164 ........................................... ................................................... ................................................... ................ 83 11.4. dc c haracteristics ................................................... ................................................... .............................................85 11.5. ac c haracteristics ................................................... ................................................... .............................................86 11.5.1. eeprom smi host mode timing characteristics........ ................................................... ........................................ 86 11.5.2. eeprom smi slave mode timing characteristics....... ................................................... ........................................ 88 11.5.3. gmii/mii timing characteristics.................... ................................................... ................................................... ... 89 11.5.4. rgmii timing characteristics ....................... ................................................... ................................................... .... 93 12. mechanical dimensions .............................. ................................................... ................................................... . 96 12.1. lq164epad .......................................... ................................................... ................................................... ................. 96 12.2. lq216epad .......................................... ................................................... ................................................... ................. 97 13. ordering information ............................... ................................................... ................................................... ..98
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller viii track id: rev. pre-1.4 list of tables table 1. pin types table......................... ................................................... ................................................... 23 table 2. pin assignment table (lqfp 164)......... ................................................... ................................. 24 table 3. pin assignment table (lqfp 216)......... ................................................... ................................. 26 table 4. mdi pins................................ ................................................... ................................................... ......... 29 table 5. fiber serdes pins ....................... ................................................... ................................................. 30 table 6. gmii pins (mac5 gmii, pins) ............. ................................................... .......................................... 31 table 7. mac5 rgmii pins......................... ................................................... ................................................... 33 table 8. port 4 rgmii pins (mac4 or phy4 rgmii pi ns) ................................................ ...................... 34 table 9. mac5 mii pins (mac5 mii mac mode or mac5 mii phy mode) ..................................... ... 35 table 10. port 4 mii pins (mac4 mii mac mode, mac 4 mii phy mode, or phy4 mii pins) ...... 38 table 11. led pins............................... ................................................... ................................................... ........ 41 table 12. miscellaneous pins ..................... ................................................... ........................................... 42 table 13. configuration strapping pins (for rtl83 66s and RTL8366Sr)................................ 4 3 table 14. configuration strapping pins (only for RTL8366Sr) ......................................... ....... 44 table 15. testing pins........................... ................................................... ................................................... ... 45 table 16. power and gnd pins ..................... ................................................... ........................................... 45 table 17. media dependent interface pin mapping .. ................................................... .................. 49 table 18. flow control resolution truth table.... ................................................... .................. 51 table 19. l2 table 4-way hash index method....... ................................................... ......................... 53 table 20. reserved multicast address configuratio n table ............................................ ... 54 table 21. serdes, port4&port 5 mac mode selection ................................................... ................ 67 table 22. port 5 mac gmii mode pins ................ ................................................... ..................................... 68 table 23. mac5 rgmii pins........................ ................................................... .................................................. 6 9 table 24. port 4 mac or phy rgmii pins ........... ................................................... ................................... 69 table 25. port 5 mac mii pins .................... ................................................... ............................................... 70 table 26. port 4 mii pins ........................ ................................................... ................................................... .. 71 table 27. serdes interface mode selection ........ ................................................... .......................... 72 table 28. register descriptions .................. ................................................... ......................................... 73 table 29. register 0: control .................... ................................................... ............................................ 74 table 30. register 1: status..................... ................................................... ............................................... 75 table 31. register 2: phy identifier 1 ........... ................................................... ...................................... 76 table 32. register 3: phy identifier 2 ........... ................................................... ...................................... 76
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller ix track id: rev. pre-1.4 table 33. register 4: auto-negotiation advertisem ent ................................................ ............ 76 table 34. register 5: auto-negotiation link partn er ability......................................... ....... 77 table 35. register 6: auto-negotiation expansion. ................................................... ................... 78 table 36. register 7: auto-negotiation page trans mit register....................................... ... 78 table 37. register 8: auto-negotiation link partn er next page register...................... 79 table 38. register 9: 1000base-t control register ................................................... ..................... 79 table 39. register 10: 1000base-t status register ................................................... ....................... 80 table 40. register 15: extended status........... ................................................... ................................. 80 table 41. absolute maximum ratings ............... ................................................... ............................... 81 table 42. operating range........................ ................................................... .............................................. 81 table 43. assembly description ................... ................................................... ........................................ 82 table 44. material property ...................... ................................................... ........................................... 82 table 45. simulation conditions .................. ................................................... ....................................... 82 table 46. thermal performance of e-pad lqfp216 on 4l/2l pcb under still air convention ......................................... ................................................... ................................................... .. 83 table 47. thermal performance of e-pad lqfp216 on 4l pcb under forced convection ......................................... ................................................... ................................................... .. 83 table 48. assembly description ................... ................................................... ........................................ 83 table 49. material property ...................... ................................................... ........................................... 84 table 50. simulation conditions .................. ................................................... ....................................... 84 table 51. thermal performance of e-pad lqfp164 on 4l/2l pcb under still air convention ......................................... ................................................... ................................................... .. 84 table 52. thermal performance of e-pad lqfp164 on 4l/2l pcb under forced convection ......................................... ................................................... ................................................... .. 84 table 53. dc characteristics ..................... ................................................... ........................................... 85 table 54. eeprom smi host mode timing characteris tics ............................................... .......... 87 table 55. eeprom smi slave mode timing characteri stics.............................................. ......... 88 table 56. gmii timing characteristics ............ ................................................... ................................. 89 table 57. mii mac mode timing characteristics .... ................................................... ..................... 91 table 58. mii phy mode timing characteristics.... ................................................... ....................... 92 table 59. rgmii timing characteristics........... ................................................... ................................ 95 table 60. ordering information................... ................................................... ....................................... 98
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller x track id: rev. pre-1.4 list of figures corrected the smi signal description of figure 1. & figure 2. ......................................... ....... iii figure 3. block diagram of RTL8366S/sr ........... ................................................... ................................ 16 figure 4. 5-port 1000base-t switch............... ................................................... ........................................ 17 figure 5. 5-port 1000base-t switch, port 4 with 1 000base-t/1000base-x ............................... .. 18 figure 6. 5-port 1000base-t router with dual mii/ rgmii interface.................................... ... 19 figure 7. 5-port 1000base-t router with one gmii interface (one arm router)............. 20 figure 8. RTL8366S lqfp-164 pin assignments...... ................................................... .............................. 21 figure 9. RTL8366Sr lqfp-216 pin assignments..... ................................................... ............................ 22 figure 10. conceptual example of polarity correct ion ................................................ ......... 49 figure 11. protocol-based vlan frame format and f low chart ........................................ 58 figure 12. RTL8366Sr max 2 -min scheduling block diagram...................... ................................. 60 figure 13. igmp&mld application example............ ................................................... ......................... 61 figure 14. floating and pull-down of single color led pins .......................................... ...... 64 figure 15. floating and pull-down of bi-color led pins .............................................. ............ 64 figure 16. smi start and stop command ............ ................................................... .............................. 65 figure 17. eeprom smi host to eeprom ............. ................................................... ................................. 65 figure 18. eeprom smi host mode frame ............ ................................................... .............................. 65 figure 19. eeprom smi sequential read............ ................................................... ................................ 66 figure 20. eeprom smi write command for slave mod e .................................................. ........... 66 figure 21. eeprom smi read command for slave mode ................................................... ............ 66 figure 22. signal diagram of mac gmii mode interf ace (1gbps) ........................................ .... 68 figure 23. signal diagram of rgmii mode interface ................................................... ................ 70 figure 24. signal diagram of mii phy mode interfa ce (100mbps)....................................... ..... 71 figure 25. 1000base-x application circuit for min i-gbic ............................................. ............... 72 figure 26. eeprom smi host mode timing characteri stics.............................................. .......... 86 figure 27. sck/sda power on timing............... ................................................... ..................................... 87 figure 28. eeprom auto-load timing............... ................................................... ................................... 87 figure 29. eeprom smi slave mode timing character istics ............................................. ........ 88 figure 30. gmii timing characteristics........... ................................................... ................................. 89 figure 31. mii mac mode timing characteristics ... ................................................... ..................... 90 figure 32. mii phy mode timing characteristics ... ................................................... ...................... 92 figure 33. rgmii output timing characteristics (m 5rg_txc_delay=0 or m4rg_txc_delay/p4rg_rxc_delay=0)................... ................................................... ....................... 93
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller xi track id: rev. pre-1.4 figure 34. rgmii output timing characteristics (m 5rg_txc_delay=1 or m4rg_txc_delay /p4rg_rxc_delay=1).................. ................................................... ....................... 94 figure 35. rgmii input timing characteristics (m5 rg_rxc_delay=0 or m4rg_rxc_delay /p4rg_txc_delay=0).................. ................................................... ....................... 94 figure 36. rgmii input timing characteristics (m5 rg_rxc_delay=1 or m4rg_rxc_delay /p4rg_txc_delay=1).................. ................................................... ....................... 94
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 12 track id: rev. pre-1.4 1. general description the RTL8366S/sr is a 164/216-pin, ultra low power; high-performance 6-port gigabit ethernet switch integrates 5-port giga-phy that support 1000base-t, 100base-t, and 10base-t. RTL8366S (lqfp-164) uses the smaller package to minimize pcb size and r tl8366sr (lqfp-216) supports more mac/phy interfaces for router and external cpu application. RTL8366S/sr integrates all the functions of a high - speed switch system including sram for packet buffering, non-blocking s witch fabric, and internal register management a single 0.13um cmos device. on ly a 25mhz crystal is required; the eeprom is optional to configure internal registers. the 5-th port mac or phy, and 6-th port mac of the RTL8366Sr implements dual mii/rgmii (or single gmii for 6-th port mac) interface for connec ting with an external phy or mac in specific applications. these interfaces could be connected t o external cpu or risc as 5-port gigabit router application. the embedded packet storage sram in the RTL8366S/sr features superior memory management technology to efficiently utilize the memory space. the RTL8366S/sr also integrates a 1k entries address look-up table with a 10-bit 4-way xor hashi ng algorithm for address searching and learning. auto aging of each entry is provided and the aging time is around 200-400 seconds. 8 filtering databas e are used to provide independent vlan learning and s hared vlan learning (ivl/svl) function. the RTL8366S/sr supports standard 802.3x flow contr ol frames for full duplex and optional backpressure for half duplex. it determines when to invoke the flow control mechanism by checking the availability of system resources, including the pac ket buffers and transmitting queues. the RTL8366S/s r supports broadcast/multicast output dropping method , which will forward broadcast/multicast packets to the non-blocked ports only. for the increasing ip m ulticast application, the RTL8366S/sr supports ipv4 igmpv1/v2/v3 and ipv6 mldv1/v2 snooping. in order to support flexible traffic classification , RTL8366S/sr supports 32-entry acl rule and multip le actions option. each port can optional to enable or disable acl rule check function. acl rule key can base on packet ingress port, destination/source mac address, 802.1q vid, 802.1q pri, ethertype field, destination/source ip address, destination/source p ort number (tcp and udp), icmp, and igmp. when acl rule matches, action configuration can choose t o drop/permit/redirect/mirror, change priority valu e in 802.1q/q tag, and rate policing. the rate polici ng mechanism supports 64kbps step up to 1gbps rate. in bridge operation, RTL8366S/sr supports 8 sets (b ased on filtering database) configurable port statu s: disable, block, learning, and forwarding for spanni ng tree protocol and multiple spanning tree protoco l. to meet the security and management application, rt l8366s/sr supports ieee 802.1x port- based/mac-based access control. for those ports tha t do not pass the ieee802.1x authentication, RTL8366S/sr also provides port-based/mac-based gues t vlan function for them to access limited network resource. 1 set port mirroring function is configured to reflect the traffic appearing on anot her
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 13 track id: rev. pre-1.4 one of switch?s port rx, or tx, or both. it also su pports many rfc mibs counters on each port for easy debug and diagnostic. to improve real-time or multimedia networking appli cations, the RTL8366S/sr supports four priority- assignment for each received packet. these are base d on (1) port based priority; (2) 802.1p/q vlan tag priority; (3) dscp field in ipv4/ipv6 header; and ( 4) acl-assigned priority. each output port supports a weighted ratio of four priority queues to fit bandw idth requirements in different applications. input bandwidth control function helps user to limit per- port traffic utilization. there are 2 leaky buckets for each queue of all ports, one for average packet rat e and the other for peak packet rate control. queue s scheduling algorithm can use strict priority (sp) o r weighted fair queue (wfq) or mixed. the RTL8366S/sr provides 4k entries vlan table for 802.1q port-based, tag-based, and protocol- based vlan operation to separate logical connectivi ty from physical connectivity. RTL8366S/sr supports 4 sets protocol-based vlan configuration, which can optional select ethertype, llc, and rfc1042 as search key. each port may be set to any topology via eeprom upon reset or eeprom smi slave interface after reset. the RTL8366S/sr also p rovides options to meet special vlan application requirements. the first option is the arp vlan func tion, which is used to select to broadcast arp frames to all vlans or only forward arp frames to t he original vlan. the second option is the leaky vlan function, which is used to select to send unic ast frames to other vlans or only forward unicast frames to the original vlan. the vlan tags can be i nserted or removed on a per port basis. in router applications, the router may want to know which input port of the incoming packet. the RTL8366S/sr supports an option to insert vlan tag w ith vid = port vid (pvid) on each egress port. the RTL8366S/sr also provides an option to admit vl an tagged packet with a specific pvid only. if this function is enabled, RTL8366S/sr will drop all non-tagged packets and packets with an incorrect pvid.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 14 track id: rev. pre-1.4 2. features single chip 6 ports gigabit non-blocking switch architecture embedded 5 ports 10/100/1000base-t phy each port supports full duplex 10/100/1000m connectivity (half duplex only supported in 10/100m mode) ieee 802.3x flow control with asymmetric flow control ability 832kbits sram for packet buffer supports maximum packet length 16k bytes jumbo frame packet forwarding and 9216 bytes with wire speed supports realtek cable testing (rtct) feature extra interface (5-th port mac or phy, and 6-th port mac) supports (only for RTL8366Sr) media independent interface (mii) gigabit media independent interface (gmii) reduced gigabit media independent interface (rgmii) port 4 support 1000base-x serdes or utp support 32-entry acl rules search keys support source port, mac, tcp, udp, ipv4, ipv6, icmp, and igmp format actions support mirror, redirect, dropping, priority adjustment, and traffic rate policing per-port can optional to enable/disable acl function and set default action when acl mismatch vlan 802.1q vlan supports for 4096 entries supports port-based, tag-based, and protocol-based vlan up to 4 protocol-based vlan entries supports per-port per-vlan egress vlan tagging and un-tagging supports svl and ivl/svl supports 1k mac address with 4-way hash algorithm supports 8 entries cam to avoid learning hash collision up to 8 filtering database supports spanning tree port status behavior configuration ieee 802.1w rapid spanning tree ieee 802.1s multiple spanning tree with up to 8 spanning tree instances supports ieee 802.1x access control protocol port-based access control mac-based access control guest vlan
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 15 track id: rev. pre-1.4 supports quality of service (qos) input bandwidth control from 64kbps to 1gbps with 64kbps step four priority queues per port per-port per-queue average and peak packet rate control scheduling supports strict priority (sp) and weighted fair queue (wfq) ieee 802.1p/q and ipv4 dscp remarking priority decision base on port, 802.1q vlan tag pri, ipv4/ipv6 dscp, and acl rule support rfc mib counter mib-ii (rfc 1213) ethernet-like mib (rfc 3635) interface group mib (rfc 2863) rmon (rfc 2819) bridge mib (rfc 1493) bridge mib extension (rfc 2674) security filtering disable learning for each port disable learning-table aging for each port drop unknown da for each port broadcast/multicast/unknown da storm control protects system from attack by hackers supports each port 3 parallel leds supports eeprom smi slave interface to access configuration register supports 2048 bytes eeprom space for configuration 25mhz crystal or 3.3v osc input support 1 interrupt output to external cpu for notification low power consumption < 500mw/port 0.13 m cmos process rtl83666s: lqfp 164-pin e-pad package RTL8366Sr: lqfp 216-pin e-pad package
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 16 track id: rev. pre-1.4 3. block diagram 3.1. block diagram of RTL8366S/sr RTL8366S/sr block diagram mii/gm ii/rgm ii giga-phy p0 gmac p1 gmac 1.25ghz serdes p2 gmac p3 gmac p4 gmac p5 gmac 832kb packet buffer sram 1k mac address table + 8 entry cam linking lists sram controller queue managment lookup engine power management controller control registers + mib counter 4096 vlan table pll 25mhz crystal power management interface sck(si_clk) /sda(si_di) pcs mux mii/gmii/r gmii i 2 c host i 2 c slave utp fiber serdes giga-phy pcs utp giga-phy pcs utp giga-phy pcs utp giga-phy pcs utp pcs mii/rg mii mux mii/rgmii mux mux figure 3. block diagram of RTL8366S/sr
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 17 track id: rev. pre-1.4 4. applications 4.1. 5 port 1000base-t switch giga mac 0 giga phy 0 giga mac 1 giga phy 1 giga mac 2 giga phy 2 giga mac 3 giga phy 3 giga mac 5 acl queue manager ale package buffer eeprom smi host/ slave address table mib counter phone-jack giga phy 4 serdes giga mac 4 figure 4. 5-port 1000base-t switch
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 18 track id: rev. pre-1.4 4.2. 5-port 1000base-t switch, 5th port support 1000base - t/1000base-x giga mac 0 giga phy 0 giga mac 1 giga phy 1 giga mac 2 giga phy 2 giga mac 3 giga phy 3 giga mac 5 acl queue manager ale package buffer address table mib counter media (tp/fiber) eeprom smi host/ slave phone-jack giga phy 4 serdes giga mac 4 figure 5. 5-port 1000base-t switch, port 4 with 100 0base-t/1000base-x
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 19 track id: rev. pre-1.4 4.3. 5 port 1000base-t router with dual mii/rgmii 4.3.1. port 5 mac and port 4 phy in mii/rgmii mode figure 6. 5-port 1000base-t router with dual mii/rg mii interface
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 20 track id: rev. pre-1.4 4.4. 5 port 1000base-t router with one gmii (one arm router) figure 7. 5-port 1000base-t router with one gmii in terface (one arm router)
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 21 track id: rev. pre-1.4 5. pin assignments 5.1. RTL8366S pin assignments (lqfp164) figure 8. RTL8366S lqfp-164 pin assignments
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 22 track id: rev. pre-1.4 5.2. RTL8366Sr pin assignments (lqfp216) RTL8366S r 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 m4rg_rxc_delay/p4rg_txc_delay/m4mm_rxd3/m4mp_txd3/p 4m_txd3 lqfp 216 e- pad package size 24mm x 24 mm en_test test_fb 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 e-pad: agnd avddh atest lpfvon dvddl pllvddl1 12 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 nc agnd lpfvop agnd mdiref agnd pllgnd1 rtt1 atestck1 rtt2 agnd p3mdiap led_p4_1 led_p4_2/reserved agnd p3mdian p3mdibp p3mdibn p3mdicp agnd agnd p1mdicn p1mdicp p2mdidn p2mdidp xxxxxxx xxxxtaiwan avddl p3mdicn p3mdidp p3mdidn p4mdiap p4mdian agnd agnd p4mdibp p4mdibn p4mdicp p4mdicn agnd p4mdidp p4mdidn xtali xtalo sel_p4mode1 sel_p4mode0 sel_p4mode2 sel_p5mode1 sel_p5mode0 sel_sdmode0 sel_sdmode1 sel_sdmode2 svddh sgnd svddt svddl sdckn sgnd sdckp sdtxn sdtxp reserved sgnd sdrxn nc nc nc nc nc nc nc nc dvddl nc reserved reserved nreset dvddio0 digital_test reserved/sck reserved/sda reserved reserved/enautoload interrupt vtestp reserved swrgnd vtestn vphtest swrgnd dvddl m5g_crs/m5rg_txd3/m5mm_col p0mdiap p0mdian p0mdibp p0mdibn p0mdicp p0mdicn p0mdidp p0mdidn p1mdiap p1mdian p1mdibp p1mdibn p1mdidp p1mdidn p2mdiap p2mdian p2mdibp p2mdibn p2mdicp p2mdicn sdrxp m5g_col/m5rg_txd2/m5mm_txd3/m5mp_rxd3 m5g_txd7/m5rg_txd1/m5mm_txd2/m5mp_rxd2 m5g_txd6/m5rg_txd0/m5mm_txd1/m5mp_rxd1 m5g_txd5/m5rg_tx_ctl/m5mm_txd0/m5mp_rxd0 m5g_txd4/m5rg_txc/m5mm_tx_en/m5mp_rx_dv m5g_txd3/m5rg_rxc/m5mm_tx_clk/m5mp_rx_clk m5g_txd2/m5rg_rx_ctl/m5mm_rx_clk/m5mp_tx_clk m5g_txd1/m5rg_rxd0/m5mm_rx_dv/m5mp_tx_en m5g_txd0/m5rg_rxd1/m5mm_rxd0/m5mp_txd0 m5g_tx_en/m5rg_rxd2/m5mm_rxd1/m5mp_txd1 m5g_gtx_clk/m5rg_rxd3/m5mm_rxd2/m5mp_txd2 m5g_tx_clk/m5rg_rxc_delay/m5mm_rxd3/m5mp_txd3 m5g_tx_er/m4rg_txc_delay/p4rg_rxc_delay/m4mm_crs/p4 m_crs m5g_rx_er/m4rg_txd3/p4rg_rxd3/m4mm_col/p4m_col m5g_rx_clk/m4rg_txd2/p4rg_rxd2/m4mm_txd3/m4mp_rxd3/ p4m_rxd3 m5g_rx_dv/m4rg_txd1/p4rg_rxd1/m4mm_txd2/m4mp_rxd2/p 4m_rxd2 m5g_rxd7/m4rg_rxd2/p4rg_txd2/m4mm_rxd1/m4mp_txd1/p4 m_txd1 m5g_rxd6/m4rg_rxd1/p4rg_txd1/m4mm_rxd0/m4mp_txd0/p4 m_txd0 m5g_rxd5/m4rg_rxd0/p4rg_txd0/m4mm_rx_dv/m4mp_tx_en/ p4m_tx_en m5g_rxd4/m4rg_rx_ctl/p4rg_tx_ctl/m4mm_rx_clk/m4mp_t x_clk/p4m_tx_clk m5g_rxd3/m4rg_rxc/p4rg_txc/m4mm_tx_clk/m4mp_rx_clk/ p4m_rx_clk m5g_rxd2/m4rg_txc/p4rg_rxc/m4mm_tx_en/m4mp_rx_dv/p4 m_rx_dv m5g_rxd1/m4rg_tx_ctl/p4rg_rx_ctl/m4mm_txd0/m4mp_rxd 0/p4m_rxd0 m5g_rxd0/m4rg_txd0/p4rg_rxd0/m4mm_txd1/m4mp_rxd1/p4 m_rxd1 m5rg_txc_delay/m5mm_crs m4rg_rxd3/p4rg_txd3/m4mm_rxd2/m4mp_txd2/p4m_txd2 led_p4_0/enblink led_p3_2/reserved led_p3_1 led_p3_0/reserved led_p2_2/reserved led_p2_1 led_p1_2/ledmod0 led_p2_0/disrtct led_p0_2/reserved led_p1_1 led_p1_0/reserved led_p0_1 led_p0_0/reserved atestck0 reserved dvddio0 dvddio0 dvddio1 dvddio1 dvddl dvddl dvddl dvddl dvddl dvddl dvddl dvddl dvddl dvddl dvddl dvddl svddl svddl avddh avddh avddh avddh avddh avddh avddh avddh avddh avddh avddh avddh avddh avddh avddl avddl avddl avddl avddl avddl avddl avddl avddl avddl avddl avddl avddl pllvddl0 agnd agnd agnd agnd agnd agnd agnd agnd agnd pllgnd0 figure 9. RTL8366Sr lqfp-216 pin assignments
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 23 track id: rev. pre-1.4 5.3. pin assignment table 5.3.1. pin type conventions upon reset: defined as a short time after the end of a hardware reset. after reset: defined as the time after the specified ?upon reset ? time. table 1. pin types table types description i input pin o output pin i/o bi-direction input/output pin a analog pin ai analog input pin ao analog output pin ai/o analog bi-direction input/output pin p digital power pin g digital ground pin ap analog power pin ag analog ground pin i pd input pin with pull-down resistor i pu input pin with pull-up resistor; (typical value = 75k ohm) o od output pin with open drain o 3s output pin with tri-state
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 24 track id: rev. pre-1.4 5.3.2. RTL8366S (lqfp164) pin assignment table table 2. pin assignment table (lqfp 164) name pin no. type name pin no. type avddl avddh atest avddh avddh lpfvop lpfvon dvddl mdiref pllgnd1 pllvddl1 avddl rtt1 rtt2 atestck1 avddh avddl p3mdiap p3mdian p3mdibp p3mdibn avddl avddh p3mdicp p3mdicn p3mdidp p3mdidn avddl avddh p4mdiap p4mdian p4mdibp p4mdibn avddl avddh p4mdicp p4mdicn p4mdidp p4mdidn avddl xtali xtalo avddh svddh sgnd svddt svddl sdckn sdckp sgnd sdtxn sdtxp svddl sckin sgnd sdrxn sdrxp svddl dvddl 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 ap ap ao ap ap ao ao p ao ag ap ap ao ao ao ap ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o ap ai ao ap ap ag ap ap ao ao ag ao ao ap ai ag ai ai ap p swrgnd dgnd nc dvddl dvddl dvddl dvddio1 nc nc nc dgnd dvddl dgnd dvddio1 dgnd dvddl dgnd led_p4_2 led_p4_1 led_p4_0/enblink led_p3_2 dvddl dvddio0 led_p3_1 led_p3_0 led_p2_2 led_p2_1 dvddl dgnd led_p1_2/ledmode0 led_p2_0 led_p0_2 led_p1_1 dvddio0 nc led_p1_0 led_p0_1 led_p0_0 dvddl dgnd dvddl avddh avddl p0mdiap p0mdian p0mdibp p0mdibn avddl avddh p0mdicp p0mdicn p0mdidp p0mdidn avddl avddh atestck0 pllgnd0 pllvddl0 avddh 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 ag g p p p p g p g p g p g i/o pu i/o pu i/o pu i/o pu p p i/o pu i/o pu i/o pu i/o pu p g i/o pu i/o pu i/o pu i/o pu p i/o pu i/o pu i/o pu p g p ap ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o ap ap ao ag ap ap
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 25 track id: rev. pre-1.4 name pin no. type name pin no. type dvddl dgnd dvddl reserved reserved nreset dvddl dvddio0 digitial_test nc sck sda dvddl dgnd vtestp reserved swrgnd vtestn reserved vphtest nc test_fb en_test 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 p g p o i/o pu i pu p p i pu i pu i/o pu p g ao ap ag ao ap ai ai ai pu avddl p1mdiap p1mdian p1mdibp p1mdibn avddl avddh p1mdicp p1mdicn p1mdidp p1mdidn avddl avddh p2mdiap p2mdian p2mdibp p2mdibn avddl avddh p2mdicp p2mdicn p2mdidp p2mdidn 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o ap ap ai/o ai/o ai/o ai/o
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 26 track id: rev. pre-1.4 5.3.3. RTL8366Sr (lqfp216) pin assignment table table 3. pin assignment table (lqfp 216) name pin no. type name pin no. type avddl avddh atest avddh avddh nc agnd lpfvop lpfvon dvddl agnd mdiref agnd pllgnd1 pllvddl1 avddl rtt1 rtt2 atestck1 agnd avddh avddl p3mdiap p3mdian agnd p3mdibp p3mdibn avddl avddh p3mdicp p3mdicn agnd agnd p3mdidp p3mdidn avddl avddh p4mdiap p4mdian agnd agnd p4mdibp p4mdibn avddl avddh p4mdicp p4mdicn agnd p4mdidp p4mdidn avddl xtali xtalo avddh sel_p4mode1 sel_p4mode0 sel_p4mode2 sel_p5mode1 sel_p5mode0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 ap ap ao ap ap ap ao ao p ag ao ag ag ap ap ao ao ao ag ap ap ai/o ai/o ag ai/o ai/o ap ap ai/o ai/o ag ag ai/o ai/o ap ap ai/o ai/o ag ag ai/o ai/o ap ap ai/o ai/o ag ai/o ai/o ap ai ao ap i pu i pu i pu i pu i pu test_fb en_test swrgnd dvddl m5g_crs/ m5rg_txd3 / m5mm_col m5g_col / m5rg_txd2 / m5mm_txd3 / m5mp_rxd3 m5g_txd7 / m5rg_txd1 / m5mm_txd2 / m5mp_rxd2 m5g_txd6 / m5rg_txd0 / m5mm_txd1 / m5mp_rxd1 m5rg_txc_delay / m5mm_crs m5g_txd5 / m5rg_tx_ctl / m5mm_txd0 / m5mp_rxd0 m5g_txd4/m5rg_txc / m5mm_tx_en/m5mp_rx_dv m5g_txd3 / m5rg_rxc / m5mm_tx_clk / m5mp_rx_clk m5g_txd2 / m5rg_rx_ctl / m5mm_rx_clk / m5mp_tx_clk m5g_txd1 / m5rg_rxd0 / m5mm_rx_dv / m5mp_tx_en dvddl dvddio1 m5g_txd0 / m5rg_rxd1 / m5mm_rxd0 / m5mp_txd0 m5g_tx_en / m5rg_rxd2 / m5mm_rxd1 / m5mp_txd1 m5g_gtx_clk / m5rg_rxd3 / m5mm_rxd2 / m5mp_txd2 m5g_tx_clk / m5rg_rxc_delay / m5mm_rxd3 / m5mp_txd3 m5g_tx_er / m4rg_txc_delay / p4rg_rxc_delay / m4mm_crs / p4m_crs m5g_rx_er / m4rg_txd3 / p4rg_rxd3 / m4mm_col / p4m_col m5g_rx_clk / m4rg_txd2 / p4rg_rxd2 / m4mm_txd3 / m4mp_rxd3 / p4m_rxd3 m5g_rx_dv / m4rg_txd1 / p4rg_rxd1 / m4mm_txd2 / m4mp_rxd2 / p4m_rxd2 m5g_rxd0 / m4rg_txd0 / p4rg_rxd0 / m4mm_txd1 / m4mp_rxd1 / p4m_rxd1 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 ai ai pu ag p i/o i/o o o i o o i/o i/o i/o p p i/o i/o i/o i/o pu i/o pu i/o i/o i/o i/o
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 27 track id: rev. pre-1.4 name pin no. type name pin no. type sel_sdmode0 sel_sdmode1 sel_sdmode2 svddh sgnd svddt svddl sdckn sdckp sgnd sdtxn sdtxp svddl sckin sgnd sdrxn sdrxp svddl nc nc nc nc nc nc nc nc dvddl nc dvddl dvddl dvddl reserved reserved nreset dvddl dvddio0 digital_test reserved / sck reserved / sda reserved reserved / enautoload interrupt dvddl vtestp reserved swrgnd vtestn reserved vphtest 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 i pu i pu i pu ap ag ap ap ao ao ag ao ao ap ai ag ai ai ap p p p p o i/o pu i pu p p i pu i pu i/o pu o i o p ao ap ag ao ap ai dvddl m5g_rxd1 / m4rg_tx_ctl / p4rg_rx_ctl / m4mm_txd0 / m4mp_rxd0 / p4m_rxd0 m5g_rxd2 / m4rg_txc / p4rg_rxc / m4mm_tx_en / m4mp_rx_dv / p4m_rx_dv m5g_rxd3 / m4rg_rxc / p4rg_txc / m4mm_tx_clk / m4mp_rx_clk / p4m_rx_clk m5g_rxd4 / m4rg_rx_ctl / p4rg_tx_ctl / m4mm_rx_clk / m4mp_tx_clk / p4m_tx_clk m5g_rxd5 / m4rg_rxd0 / p4rg_txd0 / m4mm_rx_dv / m4mp_tx_en / p4m_tx_en m5g_rxd6 / m4rg_rxd1 / p4rg_txd1 / m4mm_rxd0 / m4mp_txd0 / p4m_txd0 m5g_rxd7 / m4rg_rxd2 / p4rg_txd2 / m4mm_rxd1 / m4mp_txd1 / p4m_txd1 m4rg_rxd3 / p4rg_txd3 / m4mm_rxd2 / m4mp_txd2 / p4m_txd2 m4rg_rxc_delay / p4rg_txc_delay / m4mm_rxd3 / m4mp_txd3 /p4m_txd3 dvddio1 dvddl led_p4_2 / reserved led_p4_1 led_p4_0 / enblink led_p3_2 / reserved dvddl dvddio0 led_p3_1 led_p3_0 / reserved led_p2_2 / reserved led_p2_1 dvddl led_p1_2 / ledmod0 led_p2_0 led_p0_2 / reserved led_p1_1 dvddio0 led_p1_0 / reserved led_p0_1 led_p0_0 / reserved dvddl dvddl avddh avddl p0mdiap p0mdian agnd agnd p0mdibp p0mdibn avddl avddh 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 p i/o i/o i/o i/o i i i i i p p i/o pu i/o pu i/o pu i/o pu p p i/o pu i/o pu i/o pu i/o pu p i/o pu i/o pu i/o pu i/o pu p i/o pu i/o pu i/o pu p p ap ap ai/o ai/o ag ag ai/o ai/o ap ap
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 28 track id: rev. pre-1.4 name pin no. type name pin no. type p0mdicp p0mdicn agnd p0mdidp p0mdidn avddl avddh atestck0 pllgnd0 pllvddl0 avddh avddl p1mdiap p1mdian agnd p1mdibp p1mdibn avddl avddh p1mdicp p1mdicn agnd agnd p1mdidp p1mdidn avddl avddh p2mdiap p2mdian agnd agnd p2mdibp p2mdibn avddl avddh p2mdicp p2mdicn agnd p2mdidp p2mdidn 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 ai/o ai/o ag ai/o ai/o ap ap ao ag ap ap ap ai/o ai/o ag ai/o ai/o ap ap ai/o ai/o ag ag ai/o ai/o ap ap ai/o ai/o ag ag ai/o ai/o ap ap ai/o ai/o ag ai/o ai/o
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 29 track id: rev. pre-1.4 6. pin descriptions 6.1. media dependent interface pins table 4. mdi pins pin no. pin name lqfp 164 lqfp 216 type drive (ma) description p0mdiap/n p0mdibp/n p0mdicp/n p0mdidp/n 126 127 128 129 132 133 134 135 169 170 173 174 177 178 180 181 ai/o 10 port 0 media dependent interface a~d. for 1000base-t operation, differential data from the media is tran smitted and received on all four pairs. for 100base-tx and 10ba se-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pair has an internal 100 o hm termination resistor. p1mdiap/n p1mdibp/n p1mdicp/n p1mdidp/n 143 144 145 146 149 150 151 152 189 190 192 193 196 197 200 201 ai/o 10 port 1 media dependent interface a~d. for 1000base-t operation, differential data from the media is tran smitted and received on all four pairs. for 100base-tx and 10ba se-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pair has an internal 100 o hm termination resistor. p2mdiap/n p2mdibp/n p2mdicp/n p2mdidp/n 155 156 157 158 161 162 163 164 204 205 208 209 212 213 215 216 ai/o 10 port 2 media dependent interface a~d. for 1000base-t operation, differential data from the media is tran smitted and received on all four pairs. for 100base-tx and 10ba se-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pair has an internal 100 o hm termination resistor. p3mdiap/n p3mdibp/n p3mdicp/n p3mdidp/n 18 19 20 21 24 25 26 27 23 24 26 27 30 31 34 35 ai/o 10 port 3 media dependent interface a~d. for 1000base-t operation, differential data from the media is tran smitted and received on all four pairs. for 100base-tx and 10ba se-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pair has an internal 100 o hm termination resistor.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 30 track id: rev. pre-1.4 pin no. pin name lqfp 164 lqfp 216 type drive (ma) description p4mdiap/n p4mdibp/n p4mdicp/n p4mdidp/n 30 31 32 33 36 37 38 39 38 39 42 43 46 47 49 50 ai/o 10 port 4 media dependent interface a~d. for 1000base-t operation, differential data from the media is tran smitted and received on all four pairs. for 100base-tx and 10ba se-t operation, only mdiap/n and mdibp/n are used. auto mdix can reverse the pairs mdiap/n and mdibp/n. each of the differential pair has an internal 100 o hm termination resistor. 6.2. serdes interface pins serdes interfaces provides one port fiber interface . the interface is selected by the pulling up or do wn of sel_sdmode[1:0] pins upon power on. 6.2.1. fiber serdes pins table 5. fiber serdes pins pin no. pin name lqfp 164 lqfp 216 type description sdrxp/n 57 56 76 75 ai fiber serdes differential input: 1.25ghz serial interfaces to receive data from an external o/e module. sdtxp/n 52 51 71 70 ao fiber serdes differential output: 1.25ghz serial interfaces to transfer data to an external o/e module. sdckp/n 49 48 68 67 ao reserved for future used. sckin 54 73 ai 25mhz clock input. 6.3. general purpose interfaces (only for RTL8366Sr) RTL8366Sr (lqfp-216) supports general purpose inter faces including gmii mac, gmii phy, rgmii mac rgmii phy, mii mac, and mii phy interface s. the interfaces are selected by the pulling up or down sel_p4mode[2:0] and sel_p5mode[1:0] pins upon power on. interface selection may also be configured by register access after power on.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 31 track id: rev. pre-1.4 6.3.1. gmii pins when port 5 mac is linked at 1gbps, the interface w ill be gmii. when port 5 mac is linked at 100mbps/10mbps, the interface will be mii. 1gbps ha lf duplex is not supported in this configuration. table 6. gmii pins (mac5 gmii, pins) pin no. pin name lqf p164 lqfp 216 type drive (ma) description m5g_crs n/a 113 i/o 8 m5g_crs carrier sense input when mac5 gmii interface operation on 10/100 mii half duplex mode. m5g_crs is only valid in 10/100mbps mii half duplex mode. it is asserted high when a valid carrier is detecte d on the media. this pin must be pulled low with 1k ohm resistor wh en not used. m5g_col n/a 114 i/o 8 m5g_col collision detect input when mac5 gmii interface operation on 10/100 mii half duplex mode. m5g_col is only valid in 10/100mbps mii half duplex mode. it is asserted high when a collision is detected on the media. this pin must be pulled low with 1k ohm resistor wh en not used. m5g_txd[7:0] n/a 115 116 118 119 120 121 122 125 o 8 m5g_txd[7:0] mac5 gmii transmit data output. transmits data bus that is sent synchronously at th e rising edge of m5g_gtx_clk. in 10/100mbps mii mode, only m5g_txd[3:0] are avail able and synchronously at the rising edge of m5g_tx_clk. m5g_tx_en n/a 126 o 8 m5g_tx_en mac5 gmii transmit data enable output. transmit enable that is sent synchronously at the r ising edge of m5g_gtx_clk in gmii mode. transmit enable that is sent synchronously at the r ising edge of m5g_tx_clk in 10/100mbps mii mode. m5g_gtx_clk n/a 127 o 8 m5g_gtx_clk mac5 gmii transmit clock output. 125mhz transmit clock output when gmii is operating at 1gbps. used to synchronize m5g_txd[7:0], m5g_tx_en, and m5g_tx_er.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 32 track id: rev. pre-1.4 pin no. pin name lqf p164 lqfp 216 type drive (ma) description m5g_tx_clk n/a 128 i/o pu 8 m5g_tx_clk 2.5/25mhz transmit clock input when mac5 gmii interface operation on 10/100 mii mode. 2.5/25mhz clock driven by phy when operating in 10/100mbps mii mode. used to synchronize m5g_txd[3: 0], m5g_tx_en, and m5g_tx_er. this pin must be pulled low with 1k ohm resistor wh en not used. m5g_tx_er n/a 129 o pu 8 m5g_tx_er mac5 gmii transmit data error output. indicates that the transmit data is error. m5g_rx_er n/a 130 i m5g_rx_er mac5 gmii receive data error. indicates that the receiving data is error. the swi tch filters the receiving packet once the m5g_rx_er is asserted at the rising edge of m5g_rx_clk. valid both in 1000mbps gmii mod e and 10/100mbps mii mac mode. this pin must be pulled low with 1k ohm resistor wh en not used. m5g_rx_clk n/a 131 i m5g_rx_clk mac5 gmii receive clock input. in gmii mode: 125mhz receive clock. used to synchro nize m5g_rxd[7:0], m5g_rx_er, and m5g_rx_dv. in mii 10/100mbps mode. m5g_rxc is 2.5/25mhz. used to synchronize m5g_rxd[3:0], m5g_rx_er , m5g_rx_dv, m5g_crs, and m5g_col. this pin must be pulled low with 1k ohm resistor wh en not used. m5g_rx_dv n/a 132 i m5g_rx_dv mac5 gmii receive data valid input. receive data valid that is received synchronously a t the rising edge of m5g_rx_clk in both 1gbps gmii and 10/100mbp s mii mac mode. this pin must be pulled low with 1k ohm resistor wh en not used. m5g_rxd[7:0] n/a 141 140 139 138 137 136 135 133 i m5g_rxd[7:0] mac5 gmii receive data input. receive data bus that is received synchronously at the rising edge of m5g_rx_clk. in 10/100mbps mii mode, only m5g_rxd[3:0] are avail able. these pins must be pulled low with 1k ohm resistor when not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 33 track id: rev. pre-1.4 6.3.2. rgmii pins RTL8366Sr could support two rgmii interface when gm ii interface is disabled. table 7. mac5 rgmii pins pin no. pin name lqf p164 lqf p216 type drive (ma) description m5rg_txd[3:0] n/a 113 114 115 116 o 8 m5rg_txd[3:0] mac5 rgmii transmit data output. transmits data bus that is sent synchronously to m5 rg_txc. m5rg_tx_ctl n/a 118 o 8 m5rg_tx_ctl mac rgmii transmit control signal output. the m5rg_tx_ctl indicates mac5 tx_en at the rising edge of m5rg_txc and mac5 tx_er at the falling edge of m5rg_txc. at m5rg_txc falling edge, m5rg_tx_ctl=mac5 tx_en (xor) mac5 tx_er. m5rg_txc n/a 119 o 8 m5rg_txc mac5 rgmii transmit clock output. m5rg_txc is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for m5rg_txd[3:0] and m5rg_tx_ctl synchronization at m5rg_txc on both rising and falling edges. m5rg_rxc n/a 120 i m5rg_rxc mac5 rgmii receive clock input. m5rg_rxc is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for m5rg_rxd[3:0] and m5rg_rx_ctl synchronization at both m5rg_rxc rising and falling edge. this pin must be pulled low with 1k ohm resistor wh en not used. m5rg_rx_ctl n/a 121 i m5rg_rx_ctl mac5 rgmii receive control signal input. the m5rg_rx_ctl indicates mac5 rx_dv at the rising of m5rg_rxc and m5rg_rx_er at the falling edge of m5rg_rxc. at m5rg_rxc falling edge, m5rg_rx_ctl=mac5 rx_dv (xor) mac5 rx_er. this pin must be pulled low with 1k ohm resistor wh en not used. m5rg_rxd[3:0] n/a 127 126 125 122 i m5rg_rxd[3:0] mac5 rgmii receive data input. receive data bus that is received synchronously to m5rg_rxc. these pins must be pulled low with 1k ohm resistor when not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 34 track id: rev. pre-1.4 table 8. port 4 rgmii pins (mac4 or phy4 rgmii pi ns) pin no. pin name lqf p164 lqf p216 type drive (ma) description m4rg_txd[3:0] / p4rg_rxd[3:0] n/a 130 131 132 133 o 12 m4rg_txd[3:0] mac4 rgmii transmit data output. transmits data bus that is sent synchronously to m4 rg_txc. p4rg_rxd[3:0] phy4 rgmii receive data output. receive data bus that is sent synchronously to p4rg _rxc. m4rg_tx_ctl / p4rg_rx_ctl n/a 135 o 12 m4rg_tx_ctl mac4 rgmii transmit control signal output. the m4rg_tx_ctl indicates mac4 tx_en at the rising edge of m4rg_txc and mac4 tx_er at the falling edge of m4rg_txc. at m4rg_txc falling edge, m4rg_tx_ctl=mac4 tx_en (xor) mac4 tx_er. p4rg_rx_ctl rgmii receive control signal output. the p4rg_rx_ctl indicates phy4 rx_dv at the rising of p4rg_rxc and p4rg_rx_er at the falling edge of p4rg_rxc. at p4rg_rxc falling edge, p4rg_rx_ctl=phy4 rx_dv (xor) phy4 rx_er. m4rg_txc / p4rg_rxc n/a 136 o 12 m4rg_txc mac4 rgmii transmit clock output. m4rg_txc is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for m4rg_txd[3:0] and m4rg_tx_ctl synchronization at m4rg_txc on both rising and falling edges. p4rg_rxc phy4 rgmii receive clock output. p4rg_rxc is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for p4rg_rxd[3:0] and p4rg_rx_ctl synchronization at p4rg_rxc on both rising and falling edges. m4rg_rxc / p4rg_txc n/a 137 i m4rg_rxc mac4 rgmii receive clock input. m4rg_rxc is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for m4rg_rxd[3:0] and m4rg_rx_ctl synchronization at both m4rg_rxc rising and falling edge. phy4txc phy4 rgmii transmit clock input. p4rg_txc is 125mhz @ 1gbps, 25mhz @ 100mbps, and 2.5mhz @ 10mbps. used for p4rg_txd[3:0] and p4rg_tx_ctl synchronization at both p4rg_txc rising and falling edge. this pin must be pulled low with 1k ohm resistor wh en not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 35 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description m4rg_rx_ctl / p4rg_tx_ctl n/a 138 i m4rg_rx_ctl mac4 rgmii receive control signal input. the m4rg_rx_ctl indicates mac4 rx_dv at the rising of m4rg_rxc and mac4 rx_er at the falling edge of m4rg_rxc. at m4rg_rxc falling edge, m4rg_rx_ctl=mac4 rx_dv (xor) mac4 rx_er. p4rg_tx_ctl phy4 rgmii transmit control signal input. the p4rg_tx_ctl indicates phy4 tx_en at the rising edge of p4rg_txc and phy4 tx_er at the falling edge of p4rg_txc. at p4rg_txc falling edge, p4rg_tx_ctl=phy4 tx_en (xor) phy4 tx_er this pin must be pulled low with 1k ohm resistor wh en not used. m4rg_rxd[3:0] / p4rg_txd[3:0] n/a 142 141 140 139 i m4rg_rxd[3:0] mac 4 rgmii receive data input. receive data bus that is received synchronously to m4rg_rxc. p4rg_txd[3:0] phy4 rgmii transmit data input. transmits data bus that is received synchronously t o p4rg_txc. these pins must be pulled low with 1k ohm resistor when not used. 6.3.3. mii interface pins the mii interface only supports when gmii interface is disabled. table 9. mac5 mii pins (mac5 mii mac mode or mac5 mii phy mode) pin no. pin name lqf p164 lqf p216 type drive (ma) description m5mm_col n/a 113 i m5mm _col mac5 mii mac mode collision detect input when operation on 10/100 mii half duplex mode. this pin must be pulled low with 1k ohm resistor wh en not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 36 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description m5mm_crs n/a 117 i m5mm_crs mac5 mii mac mode carrier sense input when operation on 10/100 mii half duplex mode. this pin must be pulled low with 1k ohm resistor wh en not used. m5mm_txd[3:0] / m5mp_rxd[3:0] n/a 114 115 116 118 o 8 m5mm_txd[3:0] mac5 mii mac mode transmit data output. transmits data bus that is sent synchronously at th e rising edge of m5mm_tx_clk. m5mp_rxd[3:0] mac5 mii phy mode receive data output. receive data bus that is sent synchronously at the rising edge of m5mp_rx_clk. m5mm_tx_en / m5mp_rx_dv n/a 119 o 8 m4mm_tx_en mac5 mii mac mode transmit data enable output. transmit enable that is sent synchronously at the r ising edge of m5mm_tx_clk. m5mp_rx_dv mac5 mii phy mode receive data valid output. receive data valid that is sent synchronously at th e rising edge of m5mp_rx_clk. m5mm_tx_clk / m5mp_rx_clk n/a 120 i/o 8 m5mm_tx_clk mac5 mii mac mode transmit clock input. in mii 100mbps, m5mm_tx_clk is 25mhz clock input. in mii 10mbps, m5mm_tx_clk is 2.5mhz clock input. used to synchronize m5mm_txd[3:0], m5mm_tx_en, and m5mm_tx_er. m5mp_rx_clk mac5 mii phy mode receive clock output. in mii 100mbps, m5mp_rx_clk is 25mhz clock output. in mii 10mbps, m5mp_rx_clk is 2.5mhz clock output. used to synchronize m5mp_rxd[3:0], m5mp_rx_dv, m5mp_rx_er, m5mp_crs, and m5mp_col. this pin must be pulled low with 1k ohm resistor wh en not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 37 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description m5mm_rx_clk / m5mp_tx_clk n/a 121 i/o 8 m5mm_rx_clk mac5 mii mac mode receive clock input. in mii 100mbps, m5mm_rx_clk is 25mhz clock input. in mii 10mbps, m5mm_rx_clk is 2.5mhz clock input. used to synchronize m5mm_rxd[3:0], m5mm_rx_dv, m5mm_tx_er , m5mp_crs, and m5mp_col. m5mp_tx_clk mac5 mii phy mode transmit clock output. in mii 100mbps, m5mp_tx_clk is 25mhz clock output. in mii 10mbps, m5mp_tx_clk is 2.5mhz clock output. used to synchronize m5mp_txd[3:0], m5mp_rx_en, and m5mp_tx_er. this pin must be pulled low with 1k ohm resistor wh en not used. m5mm_ rx_dv / m5mp_ tx_en n/a 122 i m5mm_rx_dv mac5 mii mac mode receive data valid input. receive data valid that is received synchronously a t the rising edge of m5mm_rx_clk. m5mp_tx_en mac5 mii phy mode transmit data enable input. transmit data enable that is received synchronously at the rising edge of m5mp_tx_clk. this pin must be pulled low with 1k ohm resistor wh en not used. m5mm_rxd[3:0] / m5mp_txd[3:0] n/a 128 127 126 125 i m5mm_rxd[3:0] mac5 mii mac mode receive data input. receive data that is received synchronously at the rising edge of m5mm_rx_clk. m5mp_txd[3:0] mac5 mii phy mode transmit data input. transmits data that is received synchronously at th e rising edge of m5mp_tx_clk. these pins must be pulled low with 1k ohm resistor when not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 38 track id: rev. pre-1.4 table 10. port 4 mii pins (mac4 mii mac mode, mac 4 mii phy mode, or phy4 mii pins) pin no. pin name lqf p164 lqf p216 type drive (ma) description m4mm _crs / p4m _crs n/a 129 i / o 8 m4mm_crs mac4 mii mac mode carrier sense input when operation on 10/100 mii half duplex mode. p4m_crs phy4 mii carrier sense output. p4m_crs is only valid in half duplex mode. it is as serted high when a valid carrier is detected on the media. this pin must be pulled low with 1k ohm resistor wh en not used. m4mm _col / p4m _col n/a 130 i / o 8 m4mm _col mac4 mii mac mode collision detect input when operation on 10/100 mii half duplex mode. p4m _col phy4 mii collision detect output. p4m_col is only valid in half duplex mode. it is as serted high when a collision is detected on the media. this pin must be pulled low with 1k ohm resistor wh en not used. m4mm_txd[3:0] / m4mp_rxd[3:0] / p4m_rxd[3:0] n/a 131 132 133 135 o 8 m4mm_txd[3:0] mac4 mii mac mode transmit data output. transmits data bus that is sent synchronously at th e rising edge of m4mm_tx_clk. m4mp_rxd[3:0] mac4 mii phy mode receive data output. receive data bus that is sent synchronously at the rising edge of m4mp_rx_clk. p4m_rxd[3:0] phy4 mii receive data output. receive data bus that is sent synchronously at the rising edge of p4m_rx_clk.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 39 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description m4mm_tx_en / m4mp_rx_dv / p4m_rx_dv n/a 136 o 8 m4mm_tx_en mac4 mii mac mode transmit data enable output. transmit enable that is sent synchronously at the r ising edge of m4mm_tx_clk. m4mp_rx_dv mac4 mii phy mode receive data valid output. receive data valid that is sent synchronously at th e rising edge of m4mp_rx_clk. p4m_rx_dv phy4 mii receive data valid output. receive data valid that is sent synchronously at th e rising edge of p4m_rx_clk. m4mm_tx_clk / m4mp_rx_clk / p4m_rx_clk n/a 137 i/o 8 m4mm_tx_clk mac4 mii mac mode transmit clock input. in mii 100mbps, m4mm_tx_clk is 25mhz clock input. in mii 10mbps, m4mm_tx_clk is 2.5mhz clock input. used to synchronize m4mm_txd[3:0], m4mm_tx_en, and m4mm_tx_er. m4mp_rx_clk mac4 mii phy mode receive clock output. in mii 100mbps, m4mp_rx_clk is 25mhz clock output. in mii 10mbps, m4mp_rx_clk is 2.5mhz clock output. used to synchronize m4mp_rxd[3:0], m4mp_rx_dv, m4mp_rx_er, m4mp_crs, and m4mp_col. p4m_rx_clk phy4 mii mode receive clock output. in mii 100mbps, p4m_rx_clk is 25mhz clock output. in mii 10mbps, p4m_rx_clk is 2.5mhz clock output. used to synchronize p4m_rxd[3:0], p4m_rx_dv, p4m_rx_er, p4m_crs, and p4m_col. this pin must be pulled low with 1k ohm resistor wh en not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 40 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description m4mm_rx_clk / m4mp_tx_clk / p4m_tx_clk n/a 138 i/o 8 m4mm_rx_clk mac4 mii mac mode receive clock input. in mii 100mbps, m4mm_rx_clk is 25mhz clock input. in mii 10mbps, m4mm_rx_clk is 2.5mhz clock input. used to synchronize m4mm_rxd[3:0], m4mm_rx_dv, m4mm_tx_er , m4mp_crs, and m4mp_col. m4mp_tx_clk mac4 mii phy mode transmit clock output. in mii 100mbps, m4mp_tx_clk is 25mhz clock output. in mii 10mbps, m4mp_tx_clk is 2.5mhz clock output. used to synchronize m4mp_txd[3:0], m4mp_rx_en, and m4mp_tx_er. p4m_tx_clk phy4 mii mode transmit clock output. in mii 100mbps, p4m_tx_clk is 25mhz clock output. in mii 10mbps, p4m_tx_clk is 2.5mhz clock output. used to synchronize p4m_txd[3:0], p4m_tx_en, and p4m_tx_er. this pin must be pulled low with 1k ohm resistor wh en not used. m4mm_ rx_dv / m4mp_ tx_en / p4m_ tx_en n/a 139 i m4mm_rx_dv mac4 mii mac mode receive data valid input. receive data valid that is received synchronously a t the rising edge of m4mm_rx_clk. m4mp_tx_en mac4 mii phy mode transmit data enable input. transmit data enable that is received synchronously at the rising edge of m4mp_tx_clk. p4m_tx_en phy4 mii transmit data enable input. transmit data enable that is received synchronously at the rising edge of p4m_tx_clk. this pin must be pulled low with 1k ohm resistor wh en not used.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 41 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description m4mm_rxd[3:0] / m4mp_txd[3:0] / p4m_txd[3:0] n/a 143 142 141 140 i m4mm_rxd[3:0] mac4 mii mac mode receive data input. receive data that is received synchronously at the rising edge of m4mm_rx_clk. m4mp_txd[3:0] mac4 mii phy mode transmit data input. transmits data that is received synchronously at th e rising edge of m4mp_tx_clk. p4m_txd[3:0] phy4 mii transmit data input. transmits data that is received synchronously at th e rising edge of p4m_tx_clk. these pins must be pulled low with 1k ohm resistor when not used. 6.4. led pins table 11. led pins pin no. pin name lqf p164 lqf p216 type drive (ma) description led_p4_2 / reserved 100 146 i/o pu 8 port 4 led_2 output signal. note: this pin must be pulled low for normal operat ion and the led output polarity will change from low active to high active. please see section 8.20 for more detail. led_p4_1 101 147 i/o pu 8 port 4 led_1 output signal. led_p4_0 / enblink 102 148 i/o pu 8 port 4 led_0 output signal. note: when enblink is pulled low, led output polari ty will change from low active to high active. please see s ection 8.20 for more detail. led_p3_2 / reserved 103 149 i/o pu 8 port 3 led_2 output signal. led_p3_1 106 152 i/o pu 8 port 3 led_1 output signal. led_p3_0 / reserved 107 153 i/o pu 8 port 3 led_0 output signal. led_p2_2 / reserved 108 154 i/o pu 8 port 2 led_2 output signal.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 42 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type drive (ma) description led_p2_1 109 155 i/o pu 8 port 2 led_1 output signal. led_p1_2 / ledmod0 112 157 i/o pu 8 port 1 led_2 output signal. note: when ledmod0 is pulled low, led output polari ty will change from low active to high active. please see s ection 8.20 for more detail. led_p2_0 / enrtct 113 158 i/o pu 8 port 2 led_0 output signal. note: when enrtct is pulled low, led output polarit y will change from low active to high active. please see s ection 8.20 for more detail. led_p0_2 / reserved 114 159 i/o pu 8 port 0 led_2 output signal. led_p1_1 115 160 i/o pu 8 port 1 led_1 output signal. led_p1_0 / reserved 118 162 i/o pu 8 port 1 led_0 output signal. led_p0_1 119 163 i/o pu 8 port 0 led_1 output signal. led_p0_0 / reserved 120 164 i/o pu 8 port 0 led_0 output signal. 6.5. miscellaneous pins table 12. miscellaneous pins pin no. pin name lqf p164 lqf p216 type description reserved 63 91 o reserved for future used, must let floating. reserved 64 92 i/o pu reserved for future used, must let floating. sck / reserved 70 97 i pu clock of eeprom smi. eeprom interface when sda / reserved 71 98 i/o pu data of eeprom smi. eeprom interface when reserved n/a 99 o pu reserved for future used, must let floating. reserved / enautoload n/a 100 i pu reserved for future used, must let floating.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 43 track id: rev. pre-1.4 pin no. pin name lqf p164 lqf p216 type description interrupt n/a 101 o interrupt output for external c pu. xtali 41 52 ai 25mhz crystal clock input and feedba ck pin. xtalo 42 53 ao 25mhz crystal clock output pin. mdiref 9 12 ao reference resistor. a 2.49k ohm (1%) resistor must be connected between mdiref and gnd. nreset 65 93 i pu system pin reset input. low active use to reset rt l8366s/sr. 6.6. configuration strapping pins table 13. configuration strapping pins (for rtl8366 s and RTL8366Sr) pin no. pin name lqfp 164 lqfp 216 type description led_p4_2 / reserved 102 148 i/o pu internal used configuration. this pin must be pulled low via external resister f or normal operation. note: this pin must be pulled low for normal operat ion and the led output polarity will change from low active to high active. please see section 8.20 for more detail. led_p4_0 / enblink 102 148 i/o pu power on led blinking configuration. pull up: enable power on led blinking (default). pull down: disable power on led blinking. note: when enblink is pulled low, led output polari ty will change from low active to high active. please see section 8.20 for more detail. led_p1_2 / ledmod0 112 157 i/o pu led mode configuration. pull up: select led mode 1. pull down: select led mode 0. note: when ledmod0 is pulled low, led output polari ty will change from low active to high active. please see section 8.20 for more detail.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 44 track id: rev. pre-1.4 pin no. pin name lqfp 164 lqfp 216 type description led_p2_0 / enrtct 113 158 i/o pu enable realtek cable tester after power on configu ration. pull up: enable power on rtct function. pull down: disable power on rtct function. note: when enrtct is pulled low, led output polarit y will change from low active to high active. please see section 8.20 for more detail. reserved / enautoload n/a 100 i pu enable eeprom auto-load after power on configurati on. pull up: enable power on auto-load function. pull down: disable power on auto-load function. table 14. configuration strapping pins (only for rt l8366sr) pin no. pin name lqfp 164 lqf p216 type description sel_p4mode[2:0] n/a 57 55 56 i pu detail description please refers to section 9.3. sel_p5mode[1:0] n/a 58 59 i pu detail description please refers to section 9.3. sel_sdmode[2:0] n/a 62 61 60 i pu detail description please refers to section 9.4. note: these pins must be pulled low for normal 5-po rt gigabit switch operation. m4rg_txc_delay / p4rg_rxc_delay n/a 129 i pu m4rg_txc_delay, mac4 rgmii txc delay configuration . use to enable txc delay 2nsec to txd[3:0] when port 4 mac or phy in rgmii mode. pull up: enable txc delay 2nsec to txd[3:0] pull down: disable txc delay to txd[3:0] m4rg_rxc_delay / p4rg_txc_delay n/a 143 i pu m4rg_rxc_delay, mac4 rgmii rxc delay configuration . use to enable rxc delay 4nsec to rxd[3:0] when port 4 mac or phy in rgmii mode. pull up: enable rxc delay 4nsec to rxd[3:0] pull down: disable rxc delay to rxd[3:0]
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 45 track id: rev. pre-1.4 pin no. pin name lqfp 164 lqf p216 type description m5rg_txc_delay n/a 117 i pu m5rg_txc_delay, mac5 rgmii txc delay configuration . use to enable txc delay 2nsec to txd[3:0] when port 5 mac in rgmii mode. pull up: enable txc delay 2nsec to txd[3:0] pull down: disable txc delay to txd[3:0] m5rg_rxc_delay n/a 128 i pu m5rg_rxc_delay, mac5 rgmii rxc delay configuration . use to enable rxc delay 2nsec to rxd[3:0] when port 5 mac in rgmii mode. pull up: enable rxc delay 2nsec to rxd[3:0] pull down: disable rxc delay to rxd[3:0] 6.7. testing pins table 15. testing pins pin no. pin name lqf p164 lqf p216 type description atest 3 3 ao reserve for internal used, must let fl oating. lpfvop 6 8 ao reserve for internal used, must let f loating. lpfvon 7 9 ao reserve for internal used, must let f loating. rtt1 13 17 ao reserve for internal used, must let f loating. rtt2 14 18 ao reserve for internal used, must let f loating. atestck0 138 184 ao reserve for internal used, must let floating. atestck1 15 19 ao reserve for internal used, must l et floating. digital_test 68 96 i pu reserve for internal used, must let floating. vtestp 74 103 ao reserve for internal used, must le t floating. vtestn 77 106 ao reserve for internal used, must le t floating. vphtest 79 108 ai reserve for internal used, must l et floating. test_fb 81 109 ai reserve for internal used, must l et floating. en_test 82 110 ai pu reserve for internal used, must be pulled down wit h 1k ohm resistor for normal application. 6.8. power and gnd pins table 16. power and gnd pins pin no. pin name lqfp164 lqfp216 type description reserved 75, 78 104, 107 ap reserved for future use d, must let floating.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 46 track id: rev. pre-1.4 pin no. pin name lqfp164 lqfp216 type description swrgnd 76, 83 105, 111 ag reserved for future used, must connect to gnd. dvddio0 67, 105, 116 95, 151, 161 p digital i/o hig h voltage power for smi, led, nreset. dvddio1 89, 96 124, 144 p digital i/o high voltage power for general purpose interfaces. dvddl 8, 59, 60, 62, 66, 72, 86, 87, 88, 94, 98, 104, 110, 121, 123 10, 86, 88, 89, 90, 94, 102, 112, 123, 134, 145, 150, 156, 165, 166 p digital low voltage power. svddh 44 63 ap serdes high voltage power. svddt 46 65 ap serdes low voltage power. svddl 47, 53, 58 66, 72, 77 ap serdes low voltage p ower. avddh 2, 4, 5, 16, 23, 29,35, 43, 124, 131, 137, 141, 148, 154, 160 2, 4, 5, 21, 29, 37, 45, 54, 167, 176, 183, 187, 195, 203, 211 ap analog high voltage power. avddl 1, 12, 17, 22, 28, 34, 40, 125, 130, 136, 142, 147, 153, 159 1, 16, 22, 28, 36, 44, 51, 168, 175, 182, 188, 194, 202, 210 ap analog low voltage power. pllvddl0 140 186 ap pll0 low voltage power. pllvddl1 11 15 ap pll1 low voltage power. agnd e-pad 7, 11, 13, 20, 25, 32, 33, 40, 41, 48, 171, 172, 179, 191, 198, 199, 206, 207, 214 ag analog gnd. pllgnd0 139 14 ag pll0 gnd. pllgnd1 10 185 ag pll1 gnd. sgnd 45, 50, 55 64, 69, 74 ag serdes gnd. dgnd e-pad, 61, 73, 84, 93, 95, 97, 99, 111, 122 e-pad g digital gnd.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 47 track id: rev. pre-1.4 7. physical layer function description 7.1. mdi interface the RTL8366S/sr embedded 5 gigabit ethernet phy in one chip. each port uses a single common mdi interface to support 1000base-t, 100base-tx, an d 10base-t. this interface consists of four signal pairs-a, b, c, and d. each signal pair consists of two bi-directional pins that can transmit and recei ve at the same time. the mdi interface has internal termi nation resistors, and therefore reduces bom cost an d pcb complexity. for 1000base-t, all four pairs are used in both directions at the same time. for 10/10 0 links and during auto-negotiation, only pairs a and b are used. 7.2. 1000base-t transmit function the 1000base-tx transmit function performs 8b/10b c oding, scrambling, 4d-pam5 encoding. these code groups are passed through a waveform-shaping f ilter to minimize emi effect, and are transmitted onto the 4-pair cat5 cable at 125mbaud/s through d/ a converter. 7.3. 1000base-t receive function input signals from the media pass through the sophi sticated on-chip hybrid circuit to subtract the transmitted signal from the input signal for effect ive reduction of near-end echo. afterwards, the received signal is processed with state-of-the-art technology, e.g., adaptive equalization, blw (basel ine wander) correction, cross-talk cancellation, echo c ancellation, timing recovery, error correction, and 4d- pam5 decoding. then, the 8-bit-wide data is recover ed and is sent to the gmii interface at a clock speed of 125mhz. the rx mac retrieves the packet da ta from the internal receive mii/gmii interface and sends it to the packet buffer manager. 7.4. 100base-tx transmit function the 100base-tx transmit function performs parallel to serial conversion, 4b/5b coding, scrambling, nrz/nrzi conversion, and mlt-3 encoding. the 5-bit serial data stream after 4b/5b coding is then scrambled as defined by the tp-pmd stream cipher fu nction to flatten the power spectrum energy such that emi effects can be reduced significantly. the scrambled seed is based on phy addresses and is unique for each port. after scrambling, the bit stream is driven into the network media in the form of mlt-3 signaling. the mlt-3 multi-level
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 48 track id: rev. pre-1.4 signaling technology moves the power spectrum energ y from high frequency to low frequency, which also reduces emi emissions. 7.5. 100base-tx receive function the receive path includes a receiver composed of an adaptive equalizer and dc restoration circuits (to compensate for an incoming distorted mlt-3 signal), an mlt-3 to nrzi and nrzi to nrz converter to convert analog signals to digital bit-stream, an d a pll circuit to clock data bits with minimum bit error rate. a de-scrambler, 5b/4b decoder, and seri al-to-parallel conversion circuits are followed by the pll circuit. finally, the converted parallel data i s fed into the mac. 7.6. 10base-t transmit function the output 10base-t waveform is manchester-encoded before it is driven onto the network media. the internal filter shapes the driven signals to reduce emi emissions, eliminating the need for an externa l filter. 7.7. 10base-t receive function the manchester decoder converts the incoming serial stream to nrz data when the squelch circuit detects the signal level is above squelch level. 7.8. auto-negotiation for utp the RTL8366S/sr obtains the states of duplex, speed , and flow control ability for each port in utp mode through the auto-negotiation mechanism defined in the ieee 802.3 specifications. during auto- negotiation, each port advertises its ability to it s link partner and compares its ability with advert isements received from its link partner. by default, the rtl 8366s/sr advertises full capabilities (1000full, 100full, 100half, 10full, 10half) together with flo w control ability. 7.9. crossover detection and auto correction the RTL8366S/sr automatically determines whether or not it needs to crossover between pairs as shown in the table 17 so that an external crossover cable is not required. when connecting to another device that does not perform mdi crossover, the rtl 8366s/sr automatically switch its pin pairs when
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 49 track id: rev. pre-1.4 necessary to communicate with the remote device. wh en connecting to another device that does have mdi crossover capability, an algorithm determines w hich end performs the crossover function. the crossover detection and auto correction functio n can be disabled via register configuration. the p in mapping in mdi and mdi crossover mode is given belo w. table 17. media dependent interface pin mapping mdi mdi crossover pairs 1000base-t 100base-tx 10base-t 1000base-t 100base-tx 10base-t a a tx tx b rx rx b b rx rx a tx tx c c unused unused d unused unused d d unused unused c unused unused 7.10. polarity correction the RTL8366S/sr automatically corrects polarity err ors on the receiver pairs in the 1000base-t and 10base-t modes. in 100base-tx mode, the polarity do es not matter. in 1000base-t mode, receive polarity errors are aut omatically corrected based on the sequence of idle symbols. once the de-scrambler is locked the polari ty is also locked on all pairs. the polarity become s unlocked only when the receiver loses lock. in 10base-t mode, polarity errors are corrected bas ed on the detection of valid spaced link pulses. th e detection begins during the mdi crossover detection phase and locks when the 10base-t link up. the polarity becomes unlock when link is down. rx tx + _ + _ tx rx + _ + _ + _ RTL8366S/sr link partner figure 10. conceptual example of polarity correct ion
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 50 track id: rev. pre-1.4 8. switch function description 8.1. reset 8.1.1. hardware reset in a power-on reset, an internal power-on reset pul se will be generated and the RTL8366S/sr will start the reset initialization procedures. these are: determine various default settings via the hardware strap pins at the end of the nreset signal. auto load the configuration from eeprom if eeprom i s detected. complete the embedded sram bist process. initialize the packet buffer descriptor allocation. initialize the internal registers and prepare them to be accessed by the external cpu. 8.1.2. software reset the RTL8366S/sr supports two software resets; a chi p reset and a soft reset. 8.1.2.1 chip_reset when chip_reset is set to 0b1 (write and self clear ), the chip will take the following steps: 1. download configuration from strap pin and eeprom. 2. start embedded sram bist (built-in self test). 3. clear all the lookup and vlan tables. 4. reset all registers to default values. 5. restart the auto-negotiation process. 8.1.2.2 soft_reset when set soft_reset is set to 0b1 (write and self c lear), the chip will take the following steps: 6. clear the fifo and re-start packet buffer link list . 7. restart the auto-negotiation process.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 51 track id: rev. pre-1.4 8.2. 802.3x full duplex flow control the RTL8366S/sr supports ieee 802.3x flow control i n 10/100/1000m modes. flow control can be decided in two ways: when auto-negotiation is enabled, flow control depe nds on the result of nway. when auto-negotiation is disabled, flow control dep ends on port_abilityn[7:6] (n: 0 - 4). the RTL8366S/sr supports asymmetrical flow control in 1gbps mode. the auto-negotiation module checks the flow control ability of the phy mii regi ster 4, 9 and those of its link partner to resolve the flow control mode. the following shows the flow con trol resolution truth table. table 18. flow control resolution truth table local device link partner local device resolution local partner resolution pause asm_dir pause asm_dir 0 0 irrelevant irrelevant disable pause transmit and receive disable pause transmit and receive 0 1 0 irrelevant disable pause transmit and receive disable pause transmit and receive 0 1 1 0 disable pause transmit and receive disable pause transmit and receive 0 1 1 1 enable pause transmit disable pause receive enable pause receive disable pause transmit 1 0 0 irrelevant disable pause transmit and receive disable pause transmit and receive 1 irrelevant 1 irrelevant enable pause transmit and receive enable pause transmit and receive 1 1 0 0 disable pause transmit and receive disable pause transmit and receive 1 1 0 1 enable pause receive disable pause transmit enable pause transmit disable pause receive 8.3. half duplex flow control in half duplex mode, the csma/cd media access metho d is the means by which two or more stations share a common transmission medium. to transmit, a station waits (defers) for a quiet period on the medium (that is, no other station is transmitting) and then sends the intended message in bit-serial f orm. if the message collides with that of another statio n, then each transmitting station intentionally tra nsmits for an additional predefined period to ensure propa gation of the collision throughout the system. the station remains silent for a random amount of time (backoff) before attempting to transmit again.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 52 track id: rev. pre-1.4 when a transmission attempt has terminated due to a collision, it is retried until it is successful. t he scheduling of the retransmissions is determined by a controlled randomization process called ?truncate d binary exponential backoff?. at the end of enforcin g a collision (jamming), the switch delays before attempting to retransmit the frame. the delay is an integer multiple of slot time (512 bit times). the number of slot times to delay before the n th retransmission attempt is chosen as a uniformly di stributed random integer ?r? in the range: 0 Q r < 2 k where: k =min (n, backofflimit). the backofflimit for the rlt8366s/sr is 9. the half duplex back-off algorithm in the RTL8366S/ sr does not have the maximum retry count limitation of 16 (as defined in ieee 802.3). this m eans packets in the switch will not be dropped if t he back-off retry count is over 16. 8.3.1. back pressure mode in back-pressure mode, the RTL8366S/sr sends a 4-by te jam pattern (data=0xaa) to collide with incoming packets when congestion control is activat ed. the jam pattern collides at the fourth byte counted from the preamble. receive one packet after 48 consecutive jam collisions (data collisions are not included in the 48). 8.3.2. defer mode defer mode asserts the txen signal for 2k bytes in order to force the link partner to back-off. the ipg between two asserted txen is 56 bits. when cong estion control is activated on the ingress port, th e RTL8366S/sr will send a 4-byte jam pattern at the f irst incoming packet. the link partner will back-of f and wait to re-try. the RTL8366S/sr will start the defer signal 56 bits after the link partner starts to back-off. 8.4. search and learning when a packet is received, the RTL8366S/sr uses the destination mac address and filtering database index (fid) to search the 1k-entry look-up table. 4 8-bits mac address and 3-bits fid use hash algorithm, as the following equation, to calculate 8 bits index value. the RTL8366S/sr uses this 8-bit s index to compare the packet mac address with 4-entr y data (mac address) in look-up table, as shown in table 19. this is the ?address search?. if the d estination mac address is not found, the switch wil l broadcast the packet according to vlan configuratio n.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 53 track id: rev. pre-1.4 index[7] = mac 7 mac 15 mac 23 mac 31 mac 39 mac 47 fid 1 index[6] = mac 6 mac 14 mac 22 mac 30 mac 38 mac 46 fid 0 index[5] = mac 5 mac 13 mac 21 mac 29 mac 37 mac 45 fid 2 index[4] = mac 4 mac 12 mac 20 mac 28 mac 36 mac 44 fid 1 index[3] = mac 3 mac 11 mac 19 mac 27 mac 35 mac 43 fid 0 index[2] = mac 2 mac 10 mac 18 mac 26 mac 34 mac 42 fid 2 index[1] = mac 1 mac 9 mac 17 mac 25 mac 33 mac 41 fid 1 index[0] = mac 0 mac 8 mac 16 mac 24 mac 32 mac 40 fid 0 table 19. l2 table 4-way hash index method index entry 0 entry 1 entry 2 entry 3 0x00 mac addr 0 mac addr 1 mac addr 2 mac addr 3 0x01 mac addr 4 mac addr 5 mac addr 6 mac addr 7 0x02 mac addr 8 mac addr 9 mac addr 10 mac addr 11 ? 0xfe mac addr 1016 mac addr 1017 mac addr 1018 mac addr 1019 0xff mac addr 1020 mac addr 1021 mac addr 1022 mac addr 1023 the RTL8366S/sr then uses the source mac address an d fid of the incoming packet to hash into 8- bits index. asic compares the source mac address wi th 4-entry data (mac address) in this index. the RTL8366S/sr will update the entry with new informat ion, if one of the 4-entry matches. but, if no one match and the 4-entry are not all occupied by other mac addresses. the RTL8366S/sr will record the source mac address and ingress port number into one empty entry. this process is called ?learning?. the RTL8366S/sr supports 8-entry content address me mory (cam) to avoid look-up table hash collision. when all 4-entry in the look-up table in dex are occupied, the source mac address can be learned into one of the 8-entry cam. if both look-u p table and cam are full, the source mac address will not be learned in the RTL8366S/sr. address aging is used to keep the contents of the a ddress table correct in a dynamic network topology. the look-up engine will update the time stamp infor mation of an entry whenever the corresponding source mac address appears. an entry will be invali d (aged out) if it?s time stamp information is not refreshed by the address learning process during th e aging time period. the aging time of the RTL8366S/sr is between 200 and 400 seconds (typical is 300 seconds). 8.5. svl and ivl/svl the RTL8366S/sr supports 8 groups fid for l2 search and learning. in default operation, all vlan entries belong to the same fid. this is called shar e vlan learning (svl). if all vlan entries are
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 54 track id: rev. pre-1.4 configured into 8 different fids, then the same sou rce mac address with different fid can be learned into different look-up table entry. this is called independent and share vlan learning (ivl/svl.) 8.6. illegal frame filtering illegal frames such as crc error packets, runt pack ets (length <64 bytes), and oversize packets (length >maximum length) will be discarded by the r tl8366s/sr. the maximum packet length may be set to 1522, 1536, 1552, or 12k bytes. 8.7. ieee 802.3 reserved group addresses filtering contr ol the RTL8366S/sr supports the ability to drop/forwar d 802.1d specified reserved group mac addresses: 01-80-c2-00-00-04 to 01-80-c2-00-00-0f. the default setting enables forwarding of these reserved group mac address control frames. frames w ith group mac address 01-80-c2-00-00-01 (802.3x pause) and 01-80-c2-00-00-02 (802.3ad lacp) will always be filtered. mac address 01-80-c2- 00-00-03 is always forwarded. this function is cont rolled by rma_en[8:0] registers. table 20 shows the reserved multicast address (rma) configuration mode from 01-80-c2-00-00-00 to 01-80-c2-00- 00-2f. table 20. reserved multicast address configuration table assignment value rma_en bit bridge group address 01-80-c2-00-00-00 bit 0 0b0: normal process 0b1: trap to cpu ieee std 802.3, 1988 edition, full duplex pause ope ration 01-80-c2-00-00-01 bit 1 ieee std 802.3ad slow protocols-multicast address 0 1-80-c2-00-00-02 bit 2 ieee std 802.1x pae address 01-80-c2-00-00-03 bit 3 all lans bridge management group address 01-80-c2-0 0-00-10 bit 4 gmrp address 01-80-c2-00-00-20 bit 5 gvrp address 01-80-c2-00-00-21 bit 6 undefined 802.1 bridge address 01-80-c2-00-00-04 | 01-80-c2-00-00-0f bit 7 undefined garp address 01-80-c2-00-00-22 | 01-80-c2-00-00-2f bit 8
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 55 track id: rev. pre-1.4 8.8. broadcast/multicast/unknown da storm control the RTL8366S/sr can enable or disable per-port broa dcast/multicast/unknown da storm control by setting bc_storm_en/mc_storm_en/unda_storm_en regis ters, default are disabled. after receiving 32/64/128/255 broadcast/multicast/unknown da packets by the enabled port within a reference period, all the other broadcast/multicast /unknown da packets will be dropped. the reference period has 4 duration options by register configura tion. 8.9. port security function the RTL8366S/sr supports 3 kinds of security functi on to prevent malicious attack. per-port enable/disable sa auto-learning for the in gress packet. per-port enable/disable look-up table aging update function for the ingress packet. per-port enable/disable drop all unknown da packets . 8.10. mib counter RTL8366S/sr supports a set of counters, to support management function. mib-ii (rfc 1213) ethernet-like mib (rfc 3635) interface group mib (rfc 2863) rmon (rfc 2819) bridge mib (rfc 1493) bridge mib extension (rfc 2674) 8.11. port mirroring the RTL8366S/sr supports one set of port mirroring functions for all ports. the tx, or rx, or both tx/rx packets of the source port can be monitored f rom a mirror port.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 5 6 track id: rev. pre-1.4 8.12. vlan function the RTL8366S/sr supports 4k vlan groups. these can be configured as port-based vlans, ieee 802.1q tag-based vlans, and protocol-based vla n. two ingress filtering and egress filtering options provide flexible vlan configuration: ingress filtering option 1: the acceptable frame ty pe of the ingress process can be set to ?admit all? or ?admit all tagged?. ingress filtering option 2: ?admit? or ?discard? fr ames associated with a vlan for which that port is not in the member set. egress filtering option 1: ?forward? or ?discard? a rp broadcast frames between different vlan domain. egress filtering option 2: ?forward? or ?discard? l eaky vlan frames between different vlan domain. egress filtering option 3: ?forward? or ?discard? m ulticast vlan frames between different vlan domain. vlan tag can be inserted or removed at the output p ort. the RTL8366S/sr will insert a port vid (pvid) for untagged frames or remove the tag from t agged frames. the RTL8366S/sr also supports a special insert vlan tag function to separate traffi c from wan and lan sides in router and gateway applications. in router applications, the router may want to know which input port this packet came from. the RTL8366S/sr supports port vid (pvid) for each port and can insert a pvid in the vlan tag on egress. using this function, vid information carrie d in the vlan tag will be changed to pvid. the RTL8366S/sr also provides an option to admit vlan t agged packets with a specific pvid only. if this function is enabled, it will drop non-tagged packet s and packets with an incorrect pvid. 8.12.1. port-based vlan if the vlan function is enabled by setting register disvlan=0b0, the default vlan membership configuration by internal register is port 4 overla pped with all the other ports to form four individu al vlans. this default configuration of the vlan funct ion could be modified via an attached serial eeprom or eeprom smi slave interface. the 4k-entry vlan table designed into the RTL8366S/sr provide full flexibility for users to c onfigure the input ports to associate with differen t vlan groups. each input port can join more than one vlan group.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 57 track id: rev. pre-1.4 port-based vlan mapping is the simplest implicit ma pping rule. each ingress packet is assigned to a vlan group based on the input port. it is not neces sary to parse and inspect frames in real-time to determine their vlan association. all the packets r eceived on a given input port will be forwarded to this port?s vlan members. 8.12.2. ieee802.1q tag-based vlan the RTL8366S/sr supports 4k vlan entries to perform 802.1q tag-based vlan mapping. in 802.1q vlan mapping, the RTL8366S/sr uses a 12-bit explici t identifier in the vlan tag to associate received packets with a vlan. RTL8366S/sr compares the explicit identifier in the vlan tag with the 4k vlan table to determine the vlan association of this packet, and then forwards this packet to the member set of this vlan. two vids are reserved for special purposes. one of them is all 1?s, which is reserved and currently unused. the other is all 0?s, which indicates a priority tag. a priority-tag ged frame should be treated as an untagged frame. when ?802.1q tag aware vlan? is enabled, the RTL8366S/sr performs 802.1q tag-bas ed vlan mapping for tagged frames, but still performs port- based vlan mapping for untagged frames. if ?802.1q tag aware vlan? is disabled, the RTL8366S/s r performs only port-based vlan mapping both on non-tagged and tagged frames. the processin g flow when ?802.1q tag aware vlan? is enabled is illustrated below. two vlan ingress filtering functions are supported by the RTL8366S/sr in registers. one is the ?vlan tag admit control, which provides the ability to receive vlan-tagged frames only. untagged or priority tagged (vid=0) frames will be dropped. the other is ?vlan member set ingress filtering?, which will drop frames if the ingress port is not i n the member set. there are also four optional egress filtering funct ions. ?unicast leaky vlan? and ?arp leaky vlan? are supported by the RTL8366S/sr via register acces s. 8.12.3. protocol-based vlan the RTL8366S/sr support 4 groups protocol-based vla n configuration. the packet format can be rfc 1042, llc, and ethernet, as shown in figure 11. there are 4 tables configuration to assign the frame type and corresponding field value. take ip p acket configuration as an example, user can configure the frame type to be ?ethernet? and value to be ?0x0800?. each table will index to one of th e entry in 4k-entry vlan table. packet stream match t he protocol type and value will follow the vlan member configuration of the indexed entry to forwar d the packets.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 58 track id: rev. pre-1.4 da/sa type . ethernet da/sa length dsap/ssap . llc_other frame input type/length is 00-00 ~05-ff ? frame type = ethernet 6 bytes after type/length are aa-aa-03-00-00-00 ? frame type = rfc_1042 frame type = llc_other no no da/sa length rfc_1042 aa-aa-03 00-00-00 type . figure 11. protocol-based vlan frame format and flo w chart 8.12.4. port vid in a router application, the router may want to kno w which input port this packet came from. the RTL8366S/sr supports port vid (pvid) for each port to insert a pvid in the vlan tag for untagged or priority tagged packets on egress port. when 802 .1q tag aware vlan is enabled, vlan tag admit control is enabled, and non-pvid discard is enabled at the same time; packets with an incorrect pvid and non-tagged packets will be dropped. 8.13. qos function RTL8366S/sr could support 4 priority queues and the input bandwidth control. packet priority selection can depend on port-based priority, 802.1p/q tag-bas ed priority, ipv4/ipv6 dscp-based priority, and acl-based priority. when multiple priorities are en abled in RTL8366S/sr, the packet?s priority will be assigned base on priority selection table. each queue has 2 leaky buckets, one for average pac ket rate and one for peak packet rate. per-queue in each output port can select as strict priority ( sp) or weighted fair queue (wfq) for packet scheduling algorithm.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 59 track id: rev. pre-1.4 8.13.1. input bandwidth control input bandwidth control is to limit the input bandw idth, when input traffic is more than rx bandwidth parameter, this port will send out a ?pause on? fra me or drop the input packet depending on flow contr ol status. per-port can configure input bandwidth cont rol rate from 64kbps to 1gbps in 64kbps step. 8.13.2. priority assignment priority assignment specifies the priority of a rec eived packet according to different rules. the RTL8366S/sr can recognize the qos priority informat ion of incoming packets to give a different egress service priority. the RTL8366S/sr identifies the pr iority of packets based on several types of qos priority information: port-based priority 802.1p/q-based priority ipv4/ipv6 dscp-based priority acl-based priority 8.13.3. priority queue scheduling RTL8366S/sr supports max 2 -min packet scheduling algorithm. the packet schedu ling has three steps: 8. type i leaky bucket, which specifies the average pa cket rate of one queue; 9. type ii leaky bucket, which specifies the peak pack et rate of one queue; 10. ?weighted fair queue (wfq)?, which decides which qu eue is selected in one slot time to guarantee the minimal packet rate of one queue. in addition, each queue of each port can select str ict priority or wfq packet scheduling according to packet scheduling mode. figure 12 shows RTL8366S/sr packet scheduling block diagram.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 60 track id: rev. pre-1.4 guarantee max. guarantee min. queue 1 queue 2 queue 3 phase 1 phase 2 phase 3 figure 12. RTL8366Sr max 2 -min scheduling block diagram 8.13.4. 802.1p/q and dscp remarking the RTL8366S/sr also supports 802.1p/q and ip dscp remarking function. when packets egress from one of the 4 queues, the packet?s 802.1p/q priority and ip dscp can optional be remarked as configured value. each output queue has 3-bits 802.1p/q and 6- bits ip dscp value configuration register for whole system. 8.14. acl function RTL8366S/sr supports 32-entry acl rules. when a pac ket is received, its source port, source mac address, destination address, protocol, source ip a ddress, destination ip address, source port number, destination port number (tcp or udp packet), and et hertype code (non ip packet) are recorded and compared to application acl entry. if a received packet matched multiple entries, the entry with the least address is valid. if the entry is valid, the action bit and priority bit will be appl ied. if action bit is ?drop?, the packet will be dr opped. if action bit is ?cpu?, the packet will be trapped to cpu instead of forwarding to non cpu port except it has been determined drop by other rules (other than acl rule). if action bit is ?permit?, acl rule wil l take no effect to other rules. if action bit is ?mi rror?, the packet will be forwarded to mirror port and l2 lookup result destination port. the mirror port ind icates the port, which is configured in port mirror
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 61 track id: rev. pre-1.4 mechanism. the priority bit will take effect only i f action bit are ?cpu?, ?permit?, and ?mirror?. priority bit is used to determine the packet queue id according to priority assignment mechanism. 8.15. igmp&mld snooping function RTL8366S/sr supports igmp v1/v2/v3 and mld v1/v2 sn ooping. RTL8366S/sr can trap all igmp and mld packets to cpu port. cpu processes these pa ckets, gets the information of the ip multicast groups for all ports, and writes proper multicast e ntry to lookup table through eeprom smi. the typical application of RTL8366S/sr igmp and mld snooping function is shown in following figure: RTL8366Sr p5 cpu p3 p1 p4 mii i/f p0 normal igmp pkt (trap to cpu when reg 21.14 =1) pppoe igmp pkt (trap to cpu when reg 21.14 =1 & reg 22.4=0) pppoe mld pkt (trap to cpu when reg 21.13 =1 & reg 2 2.4=0) normal mld pkt (trap to cpu when reg 21.13 =1) when reg 21.15 = 0: p2 figure 13. igmp&mld application example 8.16. 802.1x function RTL8366S/sr supports ieee 802.1x port-based/mac-bas ed access control about security. port-based access control for each port. authorized port-based access control for each port. port-based access control direction for each port. mac-based access control for each port. mac-based access control direction. optional unauthorized behavior.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 62 track id: rev. pre-1.4 8.16.1. port-based access control when hosts connect with a switch, the switch will a sk the pc host for authenticating .the switch will transmit the information sent by the host to authen tication server for authenticating. 8.16.2. mac-based access control mac-based access control provide multi-authenticati on for logical port, every logical port represents a source mac address. there are some logical ports fo r a physical port according to mac-based access control. when a logical port is authenticated, the relevant source mac address can access the network. whether the source mac address that is not authenti cated or provided for 802.1x function will be dropped or trapped to cpu. 8.17. guest vlan when the RTL8366S/sr enables port-based or mac-base d 802.1x function and the connected pc doesn?t support 802.1x function or pass authenticat ion procedure. the RTL8366S/sr will drop all packets from this port or packets with unauthorized mac address. the RTL8366S/sr also supports one set guest vlan to allow the unauthorized ports or packets to be forwarded to a limited vlan domain. user can config ure one vlan id and member set for these unauthorized packets. 8.18. 802.1d function RTL8366S/sr supports 8 sets (based on fid) and four stares of each port for cpu implement 802.1d (stp) and 802.1s (mstp) function: disable state: the port will not receive/sent packet and not do le arning . blocking state: the port will only receive bpdu packet of spanning tree protocol, but not sent any packet and not do learning. learning state: the port will receive any packet including spanning tree bpdu, and do learning at the same time, but only sent bpdu packet . forwarding state: the port will receive/send any packet and does lea rning. RTL8366S/sr also supports per port transmission/rec eption enable/disable function, user can control pe r port state by register access.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 63 track id: rev. pre-1.4 8.19. rtct the RTL8366S/sr physical layer transceivers use dsp technology to implement realtek cable tester (rtct) feature. the rtct function could be used to detect short, open, or impedance mismatch in each differential pairs with cable length information. r tl8366s/sr also provide leds to indicator test stat us and result. 8.20. led indicator the RTL8366S/sr supports parallel leds for each por t. each port has three led indicator pins. each pin may have different indicator meanings set by pi ns ledmode[1:0]. refer to the pin descriptions for details. upon reset, the RTL8366S/sr supports chip diagnostics and led functions by blinking all leds once. this function can be disabled by asserti ng enblink to 0b0 (pull down). led_blink_rate[2:0] determines the led blinking per iod for activity and collision. there are 3 led pins have configuration strapping f unction, led_p4_2/reserved, led_p4_0/enblink, and led_p1_2/ledmode0. all of the se 3 pins are pulled up with internal resister. for led_p4_2/reserved, user must use exte rnal resister to pull down for normal operation. for led_p4_0/enblink, user can optional floating or pull down to disable or enable power on led blinking. for led_p1_2/ledmode0, user can option fl oating or pull down to select led mode. if these pins pull down, the led signals will output h igh active to turn on led. else, the led signal wil l output low active to turn on led. the reference cir cuit please refers to figure 14 and figure 15. the typical values for pull-down resistors are 10k . the led_p n _0, led_p n _1, and led_p n _2 pins are dual function pins: input operation for configuration upon reset, and output operation for led after reset. if the pin input is floating or pu ll high upon reset, the pin output is active low after rese t. otherwise, if the pin input is pulled down upon reset, the pin output is active high after reset. the led_p n _0 or led_p n _2 can combine with led_p n _1 as bi-color led. and led_p n _1 should operation at the same polarity as another bi-color led pin. for example, led_p0_1 should keep floating upon reset if led_p0_1 combine with led_p0 _2 as a bi-color led and led_p0_2 input is floating upon reset. these two led pins output is a ctive low after reset at this configuration. by the way, led_p0_1 should pull down upon reset if led_p0_1 co mbine with led_p0_2 as a bi-color led and led_p0_2 input is pull down upon reset. these two l ed pins output are active high after reset at this configuration.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 64 track id: rev. pre-1.4 figure 14. floating and pull-down of single color led pins figure 15. floating and pull-down of bi-color led pins 8.21. interrupt for external cpu the RTL8366S/sr provides one interrupt output pin t o notify external cpu for status alarm. interrupt pin output polarity can be configured by register a ccess. per-port has link-up and link-down interrupt flags with mask in configuration registers. when en able port link-up or link-down interrupt mask, the RTL8366S/sr will raise the interrupt signal to alar m external cpu. cpu can read the interrupt flag to find out which port has link-up or link down status change.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 65 track id: rev. pre-1.4 9. interface descriptions 9.1. eeprom smi host to eeprom the eeprom interface of the RTL8366S/sr uses the se rial bus eeprom serial management interface (smi). the 8k-bit 24c08 eeprom is read via the eepr om smi protocol. when the RTL8366S/sr is powered up, the RTL8366S/sr drives sck and sda to r ead the registers from the eeprom. sck sda start stop figure 16. smi start and stop command sck data in data out start acknowledge 1 8 9 figure 17. eeprom smi host to eeprom s a2 a1 a0 r w ac k control byte byte address data ac k ac k p msb msb figure 18. eeprom smi host mode frame
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 66 track id: rev. pre-1.4 figure 19. eeprom smi sequential read 9.2. eeprom smi slave for external cpu when eeprom auto-load is complete, the RTL8366S/sr registers can be accessed via sck and sda via an external cpu. the device address of the rtl8 366s/sr is 0x4. for the start and end of a write/read command, sck needs one extra clock befor e/after the start/stop signals. regiter write through eeprom smi slave interface address: 16'h0318 data: 16'h1918 sck sda 3'b100 ack by RTL8366S/sr reg_addr[7:0] msb to lsb reg_addr[15:8] msb to lsb write_data[7:0] msb to lsb write_data[15:8] msb to lsb ack by RTL8366S/sr stop start ctrl code 4'b1010 chip sel write ack by RTL8366S/sr ack by RTL8366S/sr ack by RTL8366S/sr need 1 clock need 1 clock figure 20. eeprom smi write command for slave mode regiter read through eeprom smi slave interface address: 16'h0318 data: 16'h1918 sck sda 3'b100 reg_addr[7:0] msb to lsb reg_addr[15:8] msb to lsb ack by cpu read_data[7:0] msb to lsb read_data[15:8] msb to lsb ack by cpu stop start ctrl code 4'b1010 chip sel read ack by RTL8366S/sr ack by RTL8366S/sr ack by RTL8366S/sr need 1 clock need 1 clock figure 21. eeprom smi read command for slave mode
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 67 track id: rev. pre-1.4 9.3. general purpose interface (only for RTL8366Sr) in gateway or wlan-11n router application, RTL8366S r supports dual rgmii interface, one for port 5 mac and the other is for port 4 phy (as shown in figure 6). but, in one arm router application, whic h cpu only has one mii/gmii/rgmii interface, RTL8366S r also supports port 5 mac to configure as gmii interface (as shown in figure 7). when port 5 mac is configured as gmii interface, port 4 mac or phy can?t be selected as any mii/gmii/rgmii inte rface. the following table shows the configuration mode for port 5 mac and port 4 phy. serdes, port 4, port 5 mac interface selection tabl e: table 21. serdes, port4&port 5 mac mode selection mode interface mode selection description serdes sel_sdmode[2:0] 0b001 port 4 phy or fiber by register configuration port 4 mac or phy sel_p4mode[2:0] 0b010 port 4 phy with mii (phy mode ) 0 port 5 mac sel_p5mode[2:0] 0b010 port 5 mac with rgmii serdes sel_sdmode[2:0] 0b001 port 4 phy or fiber by register configuration port 4 mac or phy sel_p4mode[2:0] 0b000 port 4 mac 1 port 5 mac sel_p5mode[2:0] 0b001 port 5 mac with rgmii serdes sel_sdmode[2:0] 0b001 port 4 phy or fiber by register configuration port 4 mac or phy sel_p4mode[2:0] 0b000 port 4 mac 2 port 5 mac sel_p5mode[2:0] 0b001 port 5 mac with gmii serdes sel_sdmode[2:0] 0b001 port 4 phy or fiber by register configuration port 4 mac or phy sel_p4mode[2:0] 0b011 port 4 phy with mii (phy mode ) 3 port 5 mac sel_p5mode[2:0] 0b011 port 5 mac with mii (phy mode ) serdes sel_sdmode[2:0] the others reserved for future used port 4 mac or phy sel_p4mode[2:0] the others reserved for future used 4 port 5 mac sel_p5mode[2:0] the others reserved for future used 9.3.1. port 5 mac gmii mode interface (1gbps) only port 5 mac can support gmii mode for one arm r outer application. when RTL8366Sr configured in this mode, switch doesn?t support por t 4 phy mii/rgmii mode.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 68 track id: rev. pre-1.4 table 22 shows the pin numbers and names in rtl8366 sr (lqfp-216) and figure 22 shows the signal diagram for port 5 mac in gmii interface. table 22. port 5 mac gmii mode pins pin no. port 5 mac gmii 113 m5g_crs 114 m5g_col 115, 116, 118, 119 m5g_txd[7:4] 120, 121, 122, 125 m5g_txd[3:0] 126 m5g_tx_en 127 m5g_gtx_clk (125mhz) 128 m5g_tx_clk (25/2.5 mhz) 129 m5g_tx_er 130 m5g_rx_er 131 m5g_rx_clk (125/25/2.5 mhz) 132 m5g_rx_dv 133, 135, 136, 137 m5g_rxd[0:3] 138, 139, 140, 141 m5g_rxd[4:7] m5g_rxd[0:7] m5g_rx_clk m5g_rx_er m5g_tx_er m5g_tx_clk m5g_gtx_clk m5g_tx_en m5g_txd[7:0] m5g_crs m5g_col txd[0:7] gtx_clk tx_er rx_er tx_clk rx_clk rx_dv rxd[7:0] col crs m5g_rx_clk m5g_tx_er m5g_rx_er m5g_rxd[0:7] m5g_rx_dv m5g_gtx_clk m5g_tx_en m5g_txd[7:0] m5g_rx_dv tx_en RTL8366Sr port 5 mac gmii mode cpu (mac) side gmii mode figure 22. signal diagram of mac gmii mode interf ace (1gbps)
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 69 track id: rev. pre-1.4 9.3.2. port 5 mac and port 4 phy rgmii mode (1gbps) port 5 mac and port 4 mac of RTL8366Sr supports rgm ii interfaces to external cpu. the pin numbers and names are shown in table 23 and table 2 4. figure 23 shows the signal diagram for port 5 mac or port 4 phy in rgmii interfaces. table 23. mac5 rgmii pins type port 5 mac rgmii 113, 114, 115, 116 m5rg_txd[3:0] 118 m5rg_tx_ctl 119 m5rg_txc 120 m5rg_rxc 121 m5rg_rx_ctl 122, 125, 126, 127 m5rg_rxd[0:3] 117 m5rg_txc_delay 128 m5rg_rxc_delay table 24. port 4 mac or phy rgmii pins type port 4 mac rgmii port 4 phy rgmii 130, 131, 132, 133 m4rg_txd[3:0] p4rg_rxd[3:0] 135 m4rg_tx_ctl p4rg_rx_ctl 136 m4rg_txc p4rg_rxc 137 m4rg_rxc p4rg_txc 138 m4rg_rx_ctl p4rg_tx_ctl 139, 140, 141, 142 m4rg_rxd[0:3] p4rg_txd[0:3] 129 m4rg_txc_delay p4rg_rxc_delay 143 m4rg_rxc_delay p4rg_txc_delay
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 70 track id: rev. pre-1.4 mxrg_txc mxrg_tx_ctl mxrg_txd[3:0] mxrg_rxc mxrg_rx_ctl mxrg_rxd[3:0] rxc rx_ctl rxd[3:0] txc tx_ctl txd[3:0] mxrg_tx_ctl mxrg_txd[3:0] mxrg_txc mxrg_rx_ctl mxrg_rxd[3:0] mxrg_txc cpu (mac) side rgmii mode RTL8366Sr port 5 mac rgmii mode figure 23. signal diagram of rgmii mode interface 9.3.3. port 5 mac and port 4 phy mii mac/phy mode interfac e (100mbps) both port 5 mac and port 4 mac of RTL8366Sr support mii mac/phy mode interfaces to external cpu. the pin numbers and names are shown in table 2 5 and table 26. figure 24 shows the signal diagram for port 5 mac or port 4 phy in mii phy mod e interface. table 25. port 5 mac mii pins type port 5 mac mii phy mode 113 n/a 117 n/a 114, 115, 116, 118 m5mp_rxd[3:0] 119 m5mp_rx_dv 120 m5mp_rx_clk 121 m5mp_tx_clk 122 m5mp_tx_en 125, 126, 127, 128 m5mp_txd[3:0]
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 71 track id: rev. pre-1.4 table 26. port 4 mii pins type port 4 mac mii mac mode port 4 phy mii 129 m4mm_crs p4m_crs 130 m4mm_col p4m_col 131, 132, 133, 135 m4mm_txd[3:0] p4m_rxd[3:0] 136 m4mm_tx_en p4m_rx_dv 137 m4mm_tx_clk p4m_rx_clk 138 m4mm_rx_clk p4m_tx_clk 139 m4mm_rx_dv p4m_tx_en 140, 141, 142, 143 m4mm_rxd[0:3] p4m_txd[0:3] mxmp_rx_dv mxmp_rxd[3:0] mxmp_tx_clk mxmp_tx_en mxmp_txd[3:0] mii mac mode mrx_dv mrxd[3:0] mtx_clk mtx_en mtxd[3:0] crs col mxmp_rx_dv mxmp_rxd[3:0] mxmp_tx_clk mxmp_tx_en mxmp_txd[3:0] mxmp_rx_clk mrx_clk mxmp_rx_clk RTL8366Sr mii phy mode figure 24. signal diagram of mii phy mode interfa ce (100mbps) 9.4. serdes interface RTL8366S and RTL8366Sr support one serdes interface for 1000base-x application. serdes interface can be enabled/disabled by pin strapping sel_sdmode [2:0]. these pins are pulled up with internal resisters, so user must connect these pins to gnd v ia 1k-ohm resister for normal 5-port gigabit switch operation. table 27 shows the configuration for ser des interface. when sel_sdmode[2:0] = 0b001, port 4 mac (5-th port) will support copper and serd es by configuration to switch the traffic toward th e higher priority interface. application diagram is s hown in figure 5. when serdes is selected in this m ode,
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 72 track id: rev. pre-1.4 port 4 mac can?t be selected as rgmii/mii phy inter face in RTL8366Sr. 1000base-x application example circuit for RTL8366S/sr is shown in figure 25. table 27. serdes interface mode selection sel_sdmode[2:0] application 0b000 disable serdes interface 5-port 1000base-tx gigabit switch. 0b001 5-th port copper or fiber by configuration. 4-port 1000base-tx with 1-port copper or fiber configuration. 0b010 ? 0b111 (default) reserved for future used. c85 100nf fb_mod0_0 fb_mod2_0 minigbic_rd+ r334 4.7k u12a mini-gbic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 veet tx_fault tx_disable mod_def2 mod_def1 mod_def0 rate_sel los veer veer veer rd- rd+ veer vccr vcct veet td+ td- veet l92 1uh10% 450ma 1210 1 2 c86 100nf minigbic_td+ fb_mod1_0 RTL8366S/sr_sdrxn l94 1uh10% 450ma 1210 1 2 c403 0.1uf 0603 los_0 minigbic_td- c379 0.1uf 0603 c87 10uf r333 4.7k RTL8366S/sr_sdtxp 3.3v r336 220 RTL8366S/sr_sdtxn r338 4.7k r335 4.7k minigbic_rd- r331 4.7k 0603 c90 10uf RTL8366S/sr_sdrxp figure 25. 1000base-x application circuit for min i-gbic
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 73 track id: rev. pre-1.4 10. register descriptions 10.1. page 0: pcs register (phy 0~4) table 28. register descriptions name page register register description default 0 control register 0x1140 1 status register 0x7949 2 phy identifier 1 0x001c 3 phy identifier 2 0xc960 4 auto-negotiation advertisement register 0x0de1 5 auto-negotiation link partner ability register 0x 0000 6 auto-negotiation expansion register 0x0004 7 auto-negotiation page transmit register 0x2001 8 auto-negotiation link partner next page register 0x0000 9 1000base-t control register 0x0f00 10 1000base-t status register 0x0000 11 reserved 0x0000 12 reserved 0x0006 13 reserved 0xf880 14 reserved 0x0000 15 extended status 0x3000 16 asic control register 0x0060 17 asic control register 0x4040 18 asic control register 0x0000 19 asic control register 0x0000 20 asic control register 0x1060 21 asic control register 0x0000 22 asic control register 0x0000 23 asic control register 0x2108 24 asic control register 0x2740 25 asic control register 0x8e00 26 asic control register 0x0040 27 asic control register 0x4013 28 asic control register 0x8409 29 asic control register 0x0000 30 asic control register 0x0123 phy 0~4 register 0 31 asic control register 0x0000
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 74 track id: rev. pre-1.4 10.1.1. register 0: control table 29. register 0: control reg.bit name mode description default 0.15 reset rw/sc 1=phy reset. 0=normal operation. this bit is self-clearing. 0 0.14 loopback (digital loopback) rw 1: enable loopback. this will loopback txd to rx d and ignore all activity on the cable media 0: normal operation this function is usable only when this phy is opera ted in 10base- t full duplex, 100base-tx full duplex, or 1000base- t full duplex. 0 0.13 speed selection[0] rw [0.6,0.13] speed selection[1:0] 11=reserved 10=1000 mbps 01=100 mbps 00=10 mbps when nway is enabled, this bit reflects the result of auto- negotiation (read only). when nway is disabled, this bit can be set through smi. (read/write). 0 0.12 auto negotiation enable rw 1: enable auto-negotiation process 0: disable auto-negotiation process this bit can be set through smi (read/write). 1 0.11 power down rw 1: power down. all functions wil l be disabled except smi function 0: normal operation 0 0.10 isolate rw 1: electrically isolates the phy fr om gmii. phy is still able to respond to mdc/mdio 0: normal operation 0 0.9 restart auto negotiation rw/sc 1: restart auto-negotiation process 0: normal operation 0 0.8 duplex mode rw 1: full duplex operation 0: half duplex operation when nway is enabled (reg0.12=1), this bit reflects the result of auto-negotiation (read only). when nway is disabled (reg0.12=0, force mode of utp or 1000base-x), this bit can be set through smi (read/ write). 1 0.7 collision test ro 1 = collision test enabled. 0 = normal operation. when set, this bit will cause the col signal to be asserted in response to the assertion of txen within 512-bit ti mes. the col signal will be de-asserted within 4-bit times in re sponse to the de- assertion of txen. 0 0.6 speed selection[1] rw see bit 13 1 0.[5:0] reserved ro reserved 000000
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 75 track id: rev. pre-1.4 10.1.2. register 1: status table 30. register 1: status reg.bit name mode description default 1.15 100base-t4 ro 0= no 100base-t4 capability. RTL8366S/sr doesn?t support 100base-t4 mode and bit should always be 0. 0 1.14 100base-tx-fd ro 1: 100base-tx full duplex cap able 0: not 100base-tx full duplex capable 1 1.13 100base-tx-hd ro 1: 100base-tx half duplex cap able 0: not 100base-tx half duplex capable 1 1.12 10base-t-fd ro 1: 10base-t full duplex capable 0: not 10base-tx full duplex capable 1 1.11 10base-t-hd ro 1: 10base-t half duplex capable 0: not 10base-tx half duplex capable 1 1.10 100base-t2-fd ro 0= no 100base-t2 full duplex capability. RTL8366S/sr doesn?t support 100base-t2 mode and thi s bit should always be 0. 0 1.9 100base-t2-hd ro 0= no 100base-t2 half duplex c apability. RTL8366S/sr doesn?t support 100base-t2 mode and thi s bit should always be 0. 0 1.8 extended status ro 1=extended status informatio n in register 15 the RTL8366S/sr always support extended status regi ster. 1 1.7 reserved ro reserved 0 1.6 mf preamble suppression ro the RTL8366S/sr will accept management frames wi th preamble suppressed. 1 1.5 auto-negotiate complete ro 1: auto-negotiation process completed. 0: auto-negotiation process not completed 0 1.4 remote fault ro/lh 1=remote fault indication fr om link partner has been detected. 0=no remote fault indication detected. this bit will remain set until it is cleared by rea ding register 1 via management interface. 0 1.3 auto-negotiation ability ro 1=auto-negotiation capable. (permanently =1) 0=without auto-negotiation capability. 1 1.2 link status ro/ll 1=link has never failed since previous read. 0=link has failed since previous read. if link fails, this bit will be set to 0 until bit is read. 0 1.1 jabber detect ro/lh 1=jabber detected. 0=no jabber detected. jabber is supported only in 10base-t mode. 0 1.0 extended capability ro 1=extended register capable. (permanently =1) 0=not extended register capable. 1
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 76 track id: rev. pre-1.4 10.1.3. register 2: phy identifier 1 the phy identifier registers #1 and #2 together for m a unique identifier for the phy section of this device. the identifier consists of a concatenation of the organizationally unique identifier (oui), th e vendor's model number and the model revision number . a phy may return a value of zero in each of the 32 bits of the phy identifier if desired. the phy i dentifier is intended to support network management . table 31. register 2: phy identifier 1 reg.bit name mode description default 2.[15:0] oui ro composed of the 3 rd to 18 th bits of the organizationally unique identifier (oui), respectively 0x001c 10.1.4. register 3: phy identifier 2 table 32. register 3: phy identifier 2 reg.bit name mode description default 3.[15:10] oui ro assigned to the 19 th through 24 th bits of the oui 110010 3.[9:4] model number ro manufacturer?s model number (16: indicates rtl8366 010110 3.[3:0] revision number ro manufacturer?s revision number (00: indicates s 0000 10.1.5. register 4: auto-negotiation advertisement this register contains the advertisement abilities of this device as they will be transmitted to its l ink partner during auto-negotiation. note: each time the link ability of the RTL8366S/sr is reconfigured, the auto-negotiation process shou ld be executed to allow the configuration to take effe ct. table 33. register 4: auto-negotiation advertisem ent reg.bit name mode description default 4.15 next page ro 1= additional next pages exchange desired. 0= no additional next pages exchange desired. 0 4.14 acknowledge ro permanently=0 0 4.13 remote fault rw 1: advertises that the rtl8366 s/sr has detected a remote fault 0: no remote fault detected 0 4.12 reserved ro reserved 0 4.11 asymmetric pause rw 1: advertises that the rtl 8366s/sr has asymmetric flow control capability. 0=without asymmetric flow control capability. 1 4.10 pause rw 1=advertises that the RTL8366S/sr has flow control capability. 0=without flow control capability. 1 4.9 100base-t4 ro 1 = 100base-t4 capable. 0 = not 100base-t4 capable. (permanently =0) 0 4.8 100base-tx-fd rw 1: 100base-tx full duplex capa ble 0: not 100base-tx full duplex capable 1 4.7 100base-tx rw 1: 100base-tx half duplex capable 0: not 100base-tx half duplex capable 1
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 77 track id: rev. pre-1.4 4.6 10base-t-fd rw 1: 10base-tx full duplex capable 0: not 10base-tx full duplex capable 1 4.5 10base-t rw 1: 10base-tx half duplex capable 0: not 10base-tx half duplex capable 1 4.[4:0] selector field ro [00001]=ieee 802.3 00001 the setting of register 4 has no effect unless auto -negotiation is restarted or link down. if 1000base-t is advertised, then the required next pages are automatically transmitted. 10.1.6. register 5: auto-negotiation link partner ability this register contains the advertised abilities of the link partner as received during auto-negotiatio n. the content changes after the successful auto-negot iation. table 34. register 5: auto-negotiation link partne r ability reg.bit name mode description default 5.15 next page ro 1: link partner desires next page transfer 0: link partner does not desire next page transfer 0 5.14 acknowledge ro 1: link partner acknowledges re ception of fast link pulse (flp) words 0: not acknowledged by link partner 0 5.13 remote fault ro 1: remote fault indicated by l ink partner 0: no remote fault indicated by link partner 0 5.12 reserved ro technology ability field received code word bit 12 0 5.11 asymmetric pause 1=asymmetric flow control su pported by link partner. 0=no asymmetric flow control supported by link part ner. when auto-negotiation is enabled, this bit reflects link partner ability. (read only) 0 5.10 pause ro 1=flow control supported by link part ner. 0=no flow control supported by link partner. when auto-negotiation is enabled, this bit reflects link partner ability. (read only) 0 5.9 100base-t4 ro 1: 100base-t4 supported by link p artner 0: 100base-t4 not supported by link partner 0 5.8 100base-tx-fd ro 1: 100base-tx full duplex supp orted by link partner 0: 100base-tx full duplex not supported by link par tner 0 5.7 100base-tx ro 1: 100base-tx half duplex support ed by link partner 0: 100base-tx half duplex not supported by link par tner 0 5.6 10base-t-fd ro 1: 10base-tx full duplex support ed by link partner 0: 10base-tx full duplex not supported by link part ner 0 5.5 10base-t ro 1: 10base-tx half duplex supported by link partner 0: 10base-tx half duplex not supported by link part ner 0 5.[4:0] selector field ro [00001]=ieee 802.3 00000
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 78 track id: rev. pre-1.4 10.1.7. register 6: auto-negotiation expansion table 35. register 6: auto-negotiation expansion reg.bit name mode description default 6.[15:5] reserved ro ignore on read 0 6.4 parallel detection fault ro /lh 1=a fault has been detected via the parallel detect ion function. 0=no fault has been detected via the parallel detec tion function. 0 6.3 link partner next page ability ro 1= link partner is next page able. 0= link partner is not next page able. 0 6.2 local next page ability ro 1= RTL8366S/sr is next page able. (permanently = 0) 1 6.1 page received ro /lh 1= a new page has been received. 0= a new page has not been received. 0 6.0 link partner auto-negotiation ability ro if auto-negotiation is enabled, this bit means: 1= link partner is auto-negotiation able. 0= link partner is not auto-negotiation able. 0 10.1.8. register 7: auto-negotiation page transmit register table 36. register 7: auto-negotiation page transm it register reg.bit name mode description default 7.15 next page rw 1=another next page desired 0=no other next page to send 0 7.14 reserved ro 1=a fault has been detected via th e parallel detection function. 0=no fault has been detected via the parallel detec tion function. 0 7.13 message page rw 1=message page 1 7.12 acknowledge 2 rw 1=local device has the abilit y to comply with the message received. 0= local device has no ability to comply with the m essage received. 0 7.11 toggle ro toggle bit 0 7.[10:0] message/unforma tted field rw content of message/unformatted page 1
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 79 track id: rev. pre-1.4 10.1.9. register 8: auto-negotiation link partner next page register table 37. register 8: auto-negotiation link partn er next page register reg.bit name mode description default 8.15 next page ro received link code word bit 15. 0 8.14 acknowledge ro received link code word bit 14. 0 8.13 message page ro received link code word bit 13 . 0 8.12 acknowledge 2 ro received link code word bit 1 2. 0 8.11 toggle ro received link code word bit 11. 0 8.[10:0] message/unforma tted field ro received link code word bit 10:0. 0 10.1.10. register 9: 1000base-t control register table 38. register 9: 1000base-t control register reg.bit name mode description default 9.[15:13] test mode rw test mode select: 000=normal mode. 001=test mode 1 ? transmit waveform test. 010=test mode 2 ? transmit jitter test in master mo de. 011=test mode 3 ? transmit jitter test in slave mod e. 100=test mode 4 ? transmitter distortion test. 101,110,111=reserved 000 9.12 master/slave manual configuration enable rw 1=enable master/slave manual configuration. 0=disable master/slave manual configuration. 0 9.11 master/slave configuration value rw 1=configure phy as master during master/slave negotiation, only when 9.12 is set to logical one. 0= configure phy as slave during master/slave negotiation, only when 9.12 is set to logical one. 1 9.10 port type rw 1=multi-port device 0=single-port device 1 9.9 1000base-t full duplex rw 1=advertise phy is 1000base-t full duplex capabl e. 0= advertise phy is not 1000base-t full duplex capa ble. 1 9.8 1000base-t half duplex rw 1=advertise phy is 1000base-t half duplex capabl e. 0= advertise phy is not 1000base-t half duplex capa ble. 0 9.[7:0] reserved rw reserved 0
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 80 track id: rev. pre-1.4 10.1.11. register 10: 1000base-t status register table 39. register 10: 1000base-t status register reg.bit name mode description default 10.15 master/slave configuration fault ro/lh/ sc 1=master/slave configuration fault detected. 0=no master/slave configuration fault detected. 0 10.14 master/slave configuration resolution ro 1=local phy configuration resolved to master0=lo cal phy configuration resolved to slave 0 10.13 local receiver status ro 1=local receiver ok. 0=local receiver not ok. 0 10.12 remote receiver status ro 1=remote receiver ok. 0= remote receiver not ok. 0 10.11 link partner 1000base-t full duplex ro 1=link partner is capable of 1000base-t full dup lex 0=link partner is not capable of 1000base-t full du plex 0 10.10 1000base-t half duplex ro 1=link partner is capable of 1000base-t half dup lex 0=link partner is not capable of 1000base-t half du plex 0 10.[9:8] reserved ro reserved 0 10.[7:0] idle error count ro/sc idle error counter. the counter stops automatically when it reaches 0xff. 0 10.1.12. register 15: extended status table 40. register 15: extended status reg.bit name mode description default 15.15 1000base-x full duplex ro 1=1000base-x full duplex capable. 0=not 1000base-x full duplex capable. 0 15.14 1000base-x half duplex ro 1=1000base-x half duplex capable. 0=not 1000base-x half duplex capable. 0 15.13 1000base-t full duplex ro 1=1000base-t full duplex capable. 0=not 1000base-t full duplex capable. 1 15.12 1000base-t half duplex ro 1=1000base-t half duplex capable. 0=not 1000base-t half duplex capable 1 15.[11:0] reserved ro reserved 0
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 81 track id: rev. pre-1.4 11. electrical characteristics 11.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which pe rmanent damage may be caused to the device, or device reliability will be affected. all voltages are specified reference to gnd unless otherwise specified. table 41. absolute maximum ratings parameter min max units maximum junction temperatures (tj) +125 c storage temperature -10 +125 c dvddio, avddh, and svddh supply referenced to dgnd, agnd and sgnd gnd-0.3 +3.63 v dvddl, avddl, svddl, and pllvddl supply referenced to dgnd, agnd, sgnd, and pllgnd gnd-0.3 +1.32 v svddt supply reference to sgnd gnd-0.3 +1.65 v digital input voltage gnd-0.3 vddio+0.3 v 11.2. recommended operating range table 42. operating range parameter min typical max units ambient operating temperature (ta) 0 - 70 c dvddio0, avddh and svddh supply voltage range 3.135 3.3 3.465 v 3.3v 3.135 3.3 3.465 2.5v 2.375 2.5 2.626 dvddio1 supply voltage range 1.5v 1.425 1.5 1.575 v dvddl, avddl, svddl, pllvddl supply voltage range 1.0 1.05 1.26 v 1.5v (internal regulator) 1.425 1.5 1.575 svddt supply voltage range 1.05v 1.0 1.05v 1.26 v
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 82 track id: rev. pre-1.4 11.3. thermal characteristics 11.3.1. lqfp 216 11.3.1.1 assembly description table 43. assembly description type e-pad lqfp216 dimension (l x w) 24 x 24 mm package thickness 1.4 mm pcb dimension (l x w) 101.6 x 114.3 mm 2 pcb thickness 1.6 mm pcb number of cu layer-pcb 2 layers (2s) -top layer: 20% coverage of cu, -bottom layer: 75% coverage of cu 4 layers (2s2p) -1st layer: 20% coverage of cu -2nd layer: 80% coverage of cu -3rd layer: 80% coverage of cu -4th layer: 75% coverage of cu 11.3.1.2 material property table 44. material property item material thermal conductivity k (w/m-k) die si 147 silver paste 1033bf 1.5 lead frame cda7025 168 package mold compound 7372 0.92 cu 400 pcb fr4 0.2 11.3.1.3 simulation conditions table 45. simulation conditions input power 3 w test board (pcb) 2l(2s)/4l (2s2p) control condition air flow = 0, 1, 2, 3 m/s
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 83 track id: rev. pre-1.4 11.3.1.4 results summaries table 46. thermal performance of e-pad lqfp216 on 4 l/2l pcb under still air convention ? ja ? jb ? jc ? jt ? jb 4l pcb 17.3 8.1 5.4 1.8 9.8 2l pcb 42.4 11.7 7.4 2.6 25.7 ja :junction to ambient thermal resistance, jb : junction to board thermal resistance, jc : junction to case thermal resistance jt : junction to top center of package thermal character ization jb : junction to bottom surface center of pcb thermal characterization table 47. thermal performance of e-pad lqfp216 on 4 l pcb under forced convection air flow (m/s) 0 1 2 3 ja 17.3 14.4 13.4 12.6 jt 1.8 2 2.3 2.6 4l pcb jb 9.8 9.4 9.3 9.2 ja 42.4 34.3 31.4 28.9 jt 2.6 3.4 4.3 4.8 2l pcb jb 25.7 24.6 24.4 24.1 11.3.2. lqfp 164 11.3.2.1 assembly description table 48. assembly description type e-pad lqfp164 dimension (l x w) 20 x 20 mm package thickness 1.4 mm pcb dimension (l x w) 85 x 100 mm pcb thickness 1.6 mm pcb number of cu layer-pcb 2-layer: all top layer cu coverage is 25% except for package gnd plane & 5 blocks shown in page 7 all bottom layer cu coverage is 75%, except for pow er jack & phone jack blocks 4-layer: all top layer cu coverage is 20% except for package gnd plane & 5 blocks shown in page 7 middle cu coverage: 80% all bottom layer cu coverage is 75%, except for pow er jack & phone jack blocks
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 84 track id: rev. pre-1.4 11.3.2.2 material property table 49. material property item material thermal conductivity k (w/m-k) die si 147 silver paste 1033bf 2.5 lead frame cda7025 168 package mold compound 7372 0.88 cu 400 pcb fr4 0.2 11.3.2.3 simulation conditions table 50. simulation conditions input power 2.7 w test board (pcb) 2l (2s) / 4l (2s2p) control condition air flow = 0, 1, 2, 3 m/s 11.3.2.4 results summaries table 51. thermal performance of e-pad lqfp164 on 4 l/2l pcb under still air convention ? ja ? jb ? jc ? jt ? jb 4l pcb 14.1 3.1 5.5 1.7 6.0 2l pcb 18.8 3.4 6.5 2.2 9.6 ja :junction to ambient thermal resistance, jb : junction to board thermal resistance, jc : junction to case thermal resistance jt : junction to top center of package thermal character ization jb : junction to bottom surface center of pcb thermal characterization table 52. thermal performance of e-pad lqfp164 on 4 l/2l pcb under forced convection air flow (m/s) 0 1 2 3 ? ja 14.1 10.9 10.0 9.5 ? jt 1.7 1.9 2.3 2.8 4l pcb ? jb 6.0 5.9 5.9 5.8 ? ja 18.8 15.2 14.1 13.4 ? jt 2.2 2.5 2.9 3.5 2l pcb ? jb 9.6 9.2 9.1 9.0
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 85 track id: rev. pre-1.4 11.4. dc characteristics table 53. dc characteristics parameter sym condition min typical max units power supply current for dvddio1 (for general purpose interface) i dvddio1 65 ma power supply current for svddh (for serdes interface) i svddh 38 ma power supply current for svddl (for serdes interface) i svddl 58 ma system idle power supply current for dvddio0 i dvddio0 5 ma power supply current for avddh i avddh 380 ma power supply current for dvddl i dvddl 149 ma power supply current for avddl (include pllvddl) i avddl 190 ma total power consumption for all ports ps 1626.5 mw 1000m active power supply current for dvddio0 i dvddio0 42 ma power supply current for avddh i avddh 284 ma power supply current for dvddl i dvddl 997 ma power supply current for avddl (include pllvddl) i avddl 519 ma total power consumption for all ports ps 2667.6 mw 100m active power supply current for dvddio0 i dvddio0 43 ma power supply current for avddh i avddh 203 ma power supply current for dvddl i dvddl 271 ma power supply current for avddl (include pllvddl) i avddl 184 ma total power consumption for all ports ps 1289.6 mw 10m active power supply current for dvddio0 i dvddio0 24 ma
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 86 track id: rev. pre-1.4 parameter sym condition min typical max units power supply current for avddh i avddh 550 ma power supply current for dvddl i dvddl 150 ma power supply current for avddl (include pllvddl) i avddl 71 ma total power consumption for all ports ps 2126.3 mw vddio = 3.3v ttl input high voltage v ih 2.0 v ttl input low voltage v il 0.8 v output high voltage v oh 2.7 v output low voltage v ol 0.6 v vddio = 1.5v ttl input high voltage v ih 1.0 v ttl input low voltage v il 0.5 v output high voltage v oh 1.1 v output low voltage v ol 0.4 v 11.5. ac characteristics 11.5.1. eeprom smi host mode timing characteristics sda data valid sck t1 t2 data valid t3 t4 t5 t6 t7 figure 26. eeprom smi host mode timing characteri stics
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 87 track id: rev. pre-1.4 t8 sck sda vdd figure 27. sck/sda power on timing sda sck data valid start condition stop condition t9 figure 28. eeprom auto-load timing table 54. eeprom smi host mode timing characteris tics symbol description i/o min typical max units t1 sck high time o - 840 - ns t2 sck low time o - 840 - ns t3 start condition setup time o - 840 - ns t4 start condition hold time o - 840 - ns t5 data hold time o - 860 - ns t6 data setup time o - 840 - ns t7 stop condition setup time o - 860 - ns t8 sck/sda active from power on o - 100 - ms t9 eeprom auto-load time o - 32 - ms
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 88 track id: rev. pre-1.4 11.5.2. eeprom smi slave mode timing characteristics sda data input sck t1 t2 t3 t4 t5 t6 t8 data output data input t7 figure 29. eeprom smi slave mode timing character istics table 55. eeprom smi slave mode timing characteri stics symbol description i/o min typical max units t1 sck high time i 4.0 - - s t2 sck low time i 4.0 - - s t3 start condition setup time i 4.0 - - s t4 start condition hold time i 4.0 - - s t5 data hold time i 5.0 - - s t6 data setup time i 250 - - ns t7 clock to data output delay o - 9 - ns t8 stop condition setup time i 4.0 - - s
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 89 track id: rev. pre-1.4 11.5.3. gmii/mii timing characteristics figure 30. gmii timing characteristics table 56. gmii timing characteristics parameter sym description/condition i/o min typical max units 1000base-t m5g_gtx_clk output cycle timing t g_tx_cyc 125mhz clock output. o 7.5 8.0 8.5 ns 1000base-t m5g_rx_clk input cycle time t g_rx_cyc 125mhz clock input. i 7.5 8.0 - ns 1000base-t m5g_txd[7:0], m5g_tx_er, and m5g_tx_en, output setup time t g_tx_su o 2.5 5.8 - ns
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 90 track id: rev. pre-1.4 parameter sym description/condition i/o min typical max units 1000base-t m5g_txd[7:0], m5g_tx_er, and m5g_tx_en, output hold time t g_tx_ho o 0.5 1.5 - ns 1000base-t m5g_rxd[7:0], m5g_rx_dv, m5g_rx_er, m5g_crs , and m5g_col input setup time t g_rx_su i 2 - - ns 1000base-t m5g_rxd[7:0], m5g_rx_dv, m5g_rx_er, m5g_crs , and m5g_col input hold time t g_rx_ho i 0 - - ns figure 31. mii mac mode timing characteristics
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 91 track id: rev. pre-1.4 table 57. mii mac mode timing characteristics parameter sym description/condition i/o min typical max units 100base-t m5mm_tx_clk, m4mm_tx_clk, m5mm_rx_clk, and m4mm_rx_clk input cycle time 1 / t mm_tx_cyc 1 / t mm_rx_cyc 25mhz clock input. i 25-100 ppm 25 25+100 ppm mhz 10base-t m5mm_tx_clk, m4mm_tx_clk, m5mm_rx_clk, and m4mm_rx_clk input cycle time t mm_tx_cyc t mm_rx_cyc 2.5mhz clock input. i 2.5-100 ppm 2.5 2.5+100 ppm mhz m5mm_tx_clk, m4mm_tx_clk to m5mm_txd[3:0], m5mm_tx_en, m4mm_txd[3:0], m4mm_tx_en, p4m_crs, p4m_col output delay time t mm_cod o 0 6 25 ns m5mm_rxd[3:0], m5mm_rx_dv, m5mm_col, m5mm_crs, m4mm_rxd[3:0], m4mm_rx_dv, m4mm_crs, m4mm_col input setup time t mm_rx_su i 10 - - ns m5mm_rxd[3:0], m5mm_rx_dv, m5mm_col, m5mm_crs, m4mm_rxd[3:0], m4mm_rx_dv, m4mm_crs, m4mm_col input hold time t mm_rx_ho i 10 - - ns
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 92 track id: rev. pre-1.4 figure 32. mii phy mode timing characteristics table 58. mii phy mode timing characteristics parameter sym description/condition i/o min typical max units 100m m5mp_rx_clk, m4mp_rx_clk/p4m_rx_clk, m5mp_tx_clk, and m4mp_tx_clk/p4m_tx_clk output cycle time 1 / t mp_rx_cyc 1 / t mp_tx_cyc 25mhz clock output. o 25-100 ppm 25 25+100 ppm mhz 10m m5mp_rx_clk, m4mp_rx_clk/p4m_rx_clk, m5mp_tx_clk, and m4mp_tx_clk/p4m_tx_clk output cycle time 1 / t mp_rx_cyc 1 / t mp_tx_cyc 2.5mhz clock output. o 2.5-100 ppm 2.5 2.5+10 0 ppm mhz
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 93 track id: rev. pre-1.4 parameter sym description/condition i/o min typical max units 100m m5mp_rxd[3:0], m5mp_rx_dv, m4mp_rxd[3:0]/p4m_rxd[3:0] , and m4mp_rx_dv/p4m_rx_dv to m5mp_rx_clk and m4mp_rx_clk/p4m_rx_clk output setup time t mp_rx_su o 10 18 - ns 100m m5mp_rxd[3:0], m5mp_rx_dv, m4mp_rxd[3:0]/p4m_rxd[3:0] , and m4mp_rx_dv/p4m_rx_dv to m5mp_rx_clk and m4mp_rx_clk/p4m_rx_clk output hold time t mp_rx_ho o 10 21.6 - ns 100m m5mp_tx_clk, m4mp_tx_clk/p4m_tx_clk clock output to m5mp_txd[3:0], m5mp_tx_en, m4mp_txd[3:0]/p4m_txd[3:0] , m4mp_tx_en/p4m_tx_en input delay time t mp_cod i 0 - 25 ns 11.5.4. rgmii timing characteristics figure 33. rgmii output timing characteristics (m5 rg_txc_delay=0 or m4rg_txc_delay/p4rg_rxc_delay=0)
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 94 track id: rev. pre-1.4 figure 34. rgmii output timing characteristics (m5 rg_txc_delay=1 or m4rg_txc_delay /p4rg_rxc_delay=1) figure 35. rgmii input timing characteristics (m5r g_rxc_delay=0 or m4rg_rxc_delay /p4rg_txc_delay=0) t m5rg_rxc, m4rg_rxc /p4rg_txc m5rg_rxd[3:0], m5rg_rx_ctl, m4rg_rxd[3:0] /p4rg_txd[3:0], m4rg_rx_ctl /p4rg_tx_ctl skewr figure 36. rgmii input timing characteristics (m5r g_rxc_delay=1 or m4rg_rxc_delay /p4rg_txc_delay=1)
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 95 track id: rev. pre-1.4 table 59. rgmii timing characteristics parameter sym description/condition i/o min typical max units 1000m m5rg_txc, m4rg_txc/p4rg_rxc output cycle time t tx_cyc 125mhz clock output. refer to figure 33. o 7.2 8 8.8 ns 100m m5rg_txc, m4rg_txc/p4rg_rxc output cycle time t tx_cyc 25mhz clock output. refer to figure 33. o 36 40 44 ns 10m m5rg_txc, m4rg_txc /p4rg_rxc output cycle time t tx_cyc 2.5mhz clock output. refer to figure 33. o 360 400 440 ns m5rg_txd[3:0], m5rg_tx_ctl , m4rg_txd[3:0]/p4rg_rxd[3:0] , m4rg_tx_ctl/p4rg_rx_ctl to m5rg_txc, m4rg_txc /p4rg_rxc output skew t skewt disable output clock delay (m5rg_txc_delay=0 or m4rg_txc_delay/p4rg_ rxc_delay=0). refer to figure 33. o -500 440 500 ps m5rg_txd[3:0], m5rg_tx_ctl, m4rg_txd[3:0]/p4rg_rxd[3:0] , m4rg_tx_ctl/p4rg_rx_ctl to m5rg_txc, m4rg_txc/p4rg_rxc output setup time t tx_su enable output clock delay (m5rg_txc_delay=1 or m4rg_txc_delay/p4rg_ rxc_delay=1). refer to figure 34. o 1.2 1.6 - ns m5rg_txd[3:0], m5rg_tx_ctl, m4rg_txd[3:0]/p4rg_rxd[3:0] , m4rg_tx_ctl, p4rg_rx_ctl to m5rg_txc, m4rg_txc /p4rg_rxc output hold time t tx_ho enable output clock delay (m5rg_txc_delay=1 or m4rg_txc_delay/p4rg_ rxc_delay=1). refer to figure 34. o 1.2 2.2 - ns m5rg_rxd[3:0], m5rg_rx_ctl, m4rg_rxd[3:0]/p4rg_txd[3:0] , m4rg_rx_ctl/p4rg_tx_ctl to m5rg_rxc, m4rg_rxc/p4rg_txc input setup time t rx_su disable input clock delay (m5rg_rxc_delay=0 or m4rg_rxc_delay/p4rg_ txc_delay=0). refer to figure 35. i 1.0 - - ns m5rg_rxd[3:0], m5rg_rx_ctl, m4rg_rxd[3:0]/p4rg_txd[3:0] , m4rg_rx_ctl /p4rg_tx_ctl to m5rg_rxc, m4rg_rxc/p4rg_txc input hold time t rx_ho disable input clock delay (m5rg_rxc_delay=0 or m4rg_rxc_delay/p4rg_t xc_delay=0). refer to figure 35. i 1.0 - - ns m5rg_rxd[3:0], m5rg_rx_ctl, m4rg_rxd[3:0]/p4rg_txd[3:0] , m4rg_rx_ctl/p4rg_tx_ctl to m5rg_rxc, m4rg_rxc/p4rg_txc input skew t skewr enable input clock delay. (m5rg_rxc_delay=1 or m4rg_rxc_delay/p4rg_ txc_delay=1). refer to figure 36. i 0 - 1.8 ns
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 96 track id: rev. pre-1.4 12. mechanical dimensions 12.1. lq164epad
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 97 track id: rev. pre-1.4 12.2. lq216epad
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 98 track id: rev. pre-1.4 13. ordering information table 60. ordering information part number package status RTL8366S-gr lq164-epad RTL8366Sr-gr lq216-epad note: 1. RTL8366S-gr is for 5-port gigabit switch applica tion. 2. RTL8366Sr-gr is for 5-port gigabit router applic ation.
RTL8366S/sr datasheet 6 -port 10/100/1000mbps single chip switch controller 99 track id: rev. pre-1.4 realtek semiconductor corp. headquarters no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan, r.o.c. tel: 886-3-5780211 fax: 886-3-5776047 www.realtek.com.tw

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